United States Patent m
Bayliss et al.
[li] 4,415,969 [45] Nov. 15, 1983
[54] MACROINSTRUCTION TRANSLATOR UNIT FOR USE IN A MICROPROCESSOR
[75] Inventors: John A. Bayliss, Portland; Stephen R.
Colley, Aloha; Roy H. Kravitz;
William S. Richardson, both of
Beaverton; Dorn K. Wilde, Aloha, all
of Oreg.; Gurdev Singh, Los Gatos,
Calif.
[73] Assignee: Intel Corporation, Santa Clara, Calif.
[21] Appl. No.: 119,433
[22] Filed: Feb. 7, 1980
[51] Int. C1.3 G06F 9/00; G06F 9/22;
G06F 9/30
[52] U.S. CI 364/200
[58] Field of Search ... 364/200 MS File, 900 MS File
[56] References Cited
U.S. PATENT DOCUMENTS
4,075,687 2/1978 Nissen et al 364/200
4,118,776 10/1978 Isomura 364/200
4,126,896 11/1978 Yamazaki 364/200
4,130,869 12/1978 Kinoshita et al 364/200
4,131,943 12/1978 Shiraogawa 364/200
Primary Examiner—Gareth D. Shaw
Assistant Examiner—John G. Mills
Attorney, Agent, or Firm—Owen L. Lamb
[57] ABSTRACT
An instruction translator unit which receives an instruction stream from a main memory of a microprocessor,
for latching data fields, for generating microinstructions necessary to emulate the function encoded in an instruction, and for transferring the data and microinstructions to a microinstruction execution unit over an output bus. The instruction unit includes an instruction decoder (ID) which interprets the fields of received instructions and generates single forced microinstructions and starting addresses of multiple-microinstruction routines. A microinstruction sequencer (MIS) accepts the forced microinstructions and the starting addresses and places on the output bus correct microinstruction sequences necessary to execute the received instruction. The microinstruction routines are stored in a read-only memory (ROM) in the MIS. The starting addresses received from the ID are used to index into and to fetch these microinstructions from the ROM. Forced microinstructions bypass the ROM and are transferred directly by the MIS to the execution unit.
The ID processes macroinstructions comprised of variable bit length fields by utilizing an extractor in conjunction with a bit pointer (BIP) for stripping off the bits comprising a particular field. The extracted field is presented to a state machine which decodes the particular field and generates data, microinstructions and starting addresses relating to the particular field for use by the MIS. The state machine then updates the BIP by the bit count of the particular field so that it points to the next field to be extracted.
13 Claims, 16 Drawing Figures
