United States Patent im
Dhong et al.
 FOLDER BITLINE DRAM HAVING ACCESS TRANSISTORS STACKED ABOVE TRENCH STORAGE CAPACITORS, EACH SUCH TRANSISTOR EMPLOYING A PLANAR SEMICONDUCTOR BODY WHICH SPANS ADJACENT CAPACITORS
 Inventors: Sang H. Dhong, Mahopac; Wei
Hwang, Armonk; Lewis M. Terman,
South Salem; Matthew R. Wordeman,
Mahopac, all of N.Y.
 Assignee: International Business Machines
Corporation, Armonk, N.Y.
 Appl. No.: 975,655
 Filed: Nov. 13,1992
Related U.S. Application Data
 Division of Ser. No. 740,758, Aug. 5, 1991, Pat. No. 5,214,603.
 Int. CI.* H01L 21/70; H01L 27/00
 U.S. CI 437/52; 437/60;
 Field of Search 437/52, 47^8,
437/60, 919; 257/68, 71, 301, 905-918
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[li] Patent Number: 5,336,629  Date of Patent: Aug. 9,1994
 References Cited
U.S. PATENT DOCUMENTS
4,649,625 3/1987 Lu 437/52
4,734,384 3/1988 Tsuchiya 437/52
4,920,065 4/1990 Chin et al 437/52
5,181,089 1/1993 Matsuo et al 257/299
Primary Examiner—Olik Chaudhuri
Assistant Examiner—H. Jey Tsai
Attorney, Agent, or Firm—Perman & Green
A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.
3 Claims, 9 Drawing Sheets