(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2001/0014047 Al
Hidaka et al. (43) Pub. Date: Aug. 16,2001
(54) SEMICONDUCTOR MEMORY DEVICE INCLUDING AN SOI SUBSTRATE
(75) Inventors: Hideto Hidaka, Hyogo (JP); Katsuhiro
Suma, Hyogo (JP); Takahiro Tsuruda,
McDERMOTT, WILL & EMERY
600 13th Street, N.W.
Washington, DC 20005-3096 (US)
(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
(21) Appl. No.: 09/816,402
(22) Filed: Mar. 26, 2001
Related U.S. Application Data
(60) Division of application No. 09/499,368, filed on Feb. 7, 2000, which is a division of application No. 09/146,031, filed on Sep. 2, 1998, now Pat. No. 6,091,647, which is a division of application No. 08/876,755, filed on Jun. 16, 1997, now Pat. No.
5,825,696, which is a continuation of application No. 08/353,276, filed on Dec. 5, 1994, now abandoned.
(30) Foreign Application Priority Data
Dec. 3, 1993 (JP) 5-304162 (P)
Sep. 1, 1994 (JP) 6-208393 (P)
Oct. 25, 1994 (JP) 6-260355 (P)
(51) Int. CI.7 G11C 7/00
(52) U.S. C I 365/205
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.