(12) United States Patent ao) Patent No.: us 6,593,931 Bi
Mastronarde et al. (45) Date of Patent: Jul. 15,2003
(54) METHOD AND APPARATUS FOR IMPROVING SYSTEM MEMORY BANDWIDTH UTILIZATION DURING GRAPHICS TRANSLATIONAL LOOKASIDE BUFFER CACHE MISS FETCH CYCLES
(75) Inventors: Josh B. Mastronarde, Sacremento, CA (US); Russell W. Dyer, El Dorado Hills, CA (US); Himanshu Sinha,
Citrus Heights, CA (US)
(73) Assignee: Intel Corporation, Santa Clara, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/452,540
(22) Filed: Dec. 1, 1999
(51) Int. CI.7 G06F 13/18
(52) U.S. CI 345/535; 345/557; 345/568;
711/205; 711/206; 711/207
(58) Field of Search 345/568, 520,
345/531, 530, 535, 557, 564, 566, 552, 140; 711/200, 202, 203-205, 206, 169, 211, 207, 213, 118
(56) References Cited
U.S. PATENT DOCUMENTS
5,831,640 A * 11/1998 Wang et al 345/552
An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.
17 Claims, 6 Drawing Sheets
