(12) United States Patent ao) Patent No.: Us 7,126,858 Bi
Yuan et al. (45) Date of Patent: Oct. 24,2006
(54) APPARATUS FOR EMULATING
ASYNCHRONOUS CLEAR IN MEMORY
STRUCTURE AND METHOD FOR
IMPLEMENTING THE SAME
(75) Inventors: Jinyong Yuan, Cupertino, CA (US);
Peter Kazarian, San Jose, CA (US)
(73) Assignee: Altera Corporation, San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 11/156,083
(22) Filed: Jun. 17, 2005
(51) Int. CI.
G11C 7/10 (2006.01)
(52) U.S. CI 365/189.02; 365/154
(58) Field of Classification Search 365/189.02,
365/240, 154, 230.02 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,038,059 A * 8/1991 Ebzery et al 327/217
Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability. The emulation includes defining the memory cell to have a registered read address input and a data output connected to an input of a multiplexer. The register connected to the read address input of the multiplexer does not include an asynchronous clear connection. The data transmitted from the memory cell to the multiplexer is output from the multiplexer when an asynchronous clear signal has not been asserted. However, the multiplexer is further connected to output either null data or a ground signal in lieu of the data transmitted from the memory cell when an asynchronous clear signal has been asserted.
20 Claims, 4 Drawing Sheets