Hiroki Tanigami, Fukuyama-shi
(JP); Masahiro Saitoh,
Fukuyama-shi (JP); Takayuki
Taniguchi, Kitakatsuragi-gun (JP)
Dec. 8, 2006 (JP)
Publication Classification
(51) Int. CI.
G11C11/00 (2006.01)
G11C11/416 (2006.01)
(52) U.S. CI 365/148; 365/189.16
(57) ABSTRACT
A semiconductor memory device comprises a memory cell array including memory cells arranged in matrix each having a selective transistor and a variable resistance element having an electric resistance changed from a first state to a second state by applying a first write voltage and from the second state to the first state by applying a second write voltage. A first write current for a first writing operation to change the electric resistance from the first state to the second state is larger than a second write current for a second writing operation to change it from the second state to the first state. A second memory cell number of memory cells subjected to the second writing operation at a time is greater than a first memory cell number of memory cells subjected to the first writing operation at a time. At least the second memory cell number is plural.
