CROSS-REFERENCE TO RELATED
This application is a divisional of application Ser. No. 09/813,724, filed Mar. 21, 2001, pending.
BACKGROUND OF THE INVENTION
1. Field of the Invention 10 The present invention relates to a semiconductor die
package. More particularly, the present invention relates to a folded interposer used to increase the semiconductor die density of a high density semiconductor package.
2. Background of Related Art 15 As electronic devices, such as cell phones and personal
digital assistants ("PDAs"), become smaller, more portable, and more technologically advanced, there is an increasing need for high density semiconductor die packages that can 2Q provide the necessary memory for these devices. New, high density semiconductor packages must be easily and cheaply manufactured with existing equipment. In addition, the package must maintain the reliability and quality of the semiconductor die. A semiconductor die package contains ^ many electrical circuit components that must be interconnected to form functional, integrated circuits.
Consumers want their portable devices to perform the same functions as their desktop computers, therefore requiring large amounts of memory in a much smaller electronic 30 device. One way of accomplishing this is to increase the density of a semiconductor die package by using the package's real estate more efficiently. One advantage of high density packaging is that it decreases the length of the connections between the semiconductor die and the 35 package, allowing the semiconductor die to respond faster. Also, reducing the length of the connections reduces the signal propagation time and makes the signal paths less vulnerable to the effects of noise.
Numerous high density semiconductor packages exist in 40 the art. However, these packages are ill-suited for use in small, portable electronic devices because they inefficiently use their real estate, which unnecessarily adds to the overall size of the package. For instance, U.S. Pat. No. 5,128,831 issued to Fox, III et al. teaches a high density package 45 composed of multiple submodules, each of which contains a chip bonded to a substrate. A spacer, which is at least as thick as the chip, is adhesively bonded to the peripheral upper surface of each submodule before the submodules are stacked to form the high density package. The thickness of 50 the spacer causes a gap between each submodule. When multiple submodules are needed, the cumulative effect of these gaps makes the package significantly larger than the size of the components used in the package.
A multichip module comprised of stacked semiconductor 55 dice is disclosed in U.S. Pat. No. 5,323,060, issued to Fogal et al. The semiconductor dice are electrically connected to a substrate by extending long bond wires from bond pads on each semiconductor die to the substrate. In order to accommodate the loop height of the bond wires, a thick adhesive 60 layer is applied between the semiconductor dice. The adhesive layer must be thick enough that the bond wires of the lower semiconductor die do not contact the upper semiconductor die. This multichip module is not suited for small electronic devices because the adhesive layer between the 65 dice increases the overall thickness of the semiconductor package.
U.S. Pat. No. 5,604,377 issued to Palagonia teaches a stack of semiconductor chips designed to be lightweight and to provide better cooling, mechanical shock, and vibration protection. The chips are separated by rigid, insulating interposers formed from a rack structure that contains shelves. The shelves provide electrical insulation and mechanical protection to the chips. The rigid shelves also prevent undue movement of the chips, while the spacing between shelves allows for adequate heat dissipation. Since the shelves are rigid and provide space between the chips, the packaging scheme is not suited for use in small electronic devices.
U.S. Pat. No. 5,818,107 issued to Pierson et al. teaches an integrated circuit package that utilizes metallization features, located at opposite edges of each chip, to attach a stack of chips to a substrate. The chips are bonded together through their metallization features to form a chip stack, which is then bonded to the substrate. The thickness of the metallization features, in addition to the bonding material used, provides a "stand off" or separation between chips. This separation adds to the overall thickness of the integrated circuit package, making it incompatible for use in electronic devices that require small semiconductor packages.
In U.S. Pat. No. 5,994,166 issued to Akram et al., a dense semiconductor package comprising multiple substrates with attached flip-chips is disclosed. The substrates are stacked on top of one another. Column-like connections positioned between the stacked substrates provide electrical communication. The electrical connections must be of sufficient height to provide enough clearance between substrates to mount components and also must be of sufficient strength to provide support between the substrates. Since the columnlike connections cause unused space between the substrates, this semiconductor package is incompatible with electronic devices that require small semiconductor packages.
While numerous high density semiconductor packages exist, they share a common disadvantage in that they inefficiently use the space of the semiconductor package. The unused or wasted space may be the result of thick adhesive layers between semiconductor dice or may be caused by rigid interposers or other spacers. Small electronic devices, such as cell phones and PDAs, have very limited space and cannot afford to waste any of this space. Reducing the wasted or unused space in a semiconductor die package is essential because large packages occupy too much of this limited space. It would be preferable to reduce the unused or wasted space in a stack of semiconductor dice by more closely spacing the semiconductor dice. It would be more preferable for the semiconductor dice to be spaced substantially one on top of another. It would be most preferable for the overall size of a high density semiconductor package to be caused only by the thickness of the semiconductor die and a substrate, without substantial thickness coming from additional packaging or unused space.
Methods for connecting dice to a substrate are well known in the art. For example, wire bonding, tape automated bonding ("TAB"), and controlled collapse chip connection ("C4") are commonly used to physically and electrically connect semiconductor dice to a substrate. Wire bonding utilizes fine wire conductors bonded on one end to the substrate and on the other end to electrical contacts on the semiconductor die. Because wire bonding requires wires to be welded to the die, there must be adequate space to accommodate the wires. TAB utilizes patterned metal on a polymeric tape to join dice together. The joined semiconductor dice are attached to a substrate by outer lead bonding.