(i9) United States
(12) Patent Application Publication oo) Pub. No.: US 2007/0152708 Al
Madurawe et al. (43) Pub. Date: Jul. 5,2007
(60) Provisional application No. 60/393,763, filed on Jul. 8, 2002. Provisional application No. 60/397,070, filed on Jul. 22, 2002.
(51) Int. CI.
H03K 19/177 (2006.01)
(52) U.S. CI 326/39
A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
(76) Inventors: Raminda Udaya Madurawe,
Sunnyvale, CA (US); Peter Ramyalal
Suaris, Danville, CA (US); Thomas
Henry White, Santa Clara, CA (US)
RAMINDA U. MADURAWE
882 LOUISE DRIVE
SUNNYVALE, CA 94087 (US)
(21) Appl. No.: 11/712,380
(22) Filed: Mar. 1, 2007
Related U.S. Application Data
(63) Continuation-in-part of application No. 11/645,313, filed on Dec. 26, 2006, which is a continuation of application No. 11/384,116, filed on Mar. 20, 2006, which is a continuation of application No. 10/825, 194, filed on Apr. 16, 2004, now Pat. No. 6,992,503, which is a continuation of application No. 10/267, 511, filed on Oct. 8, 2002, now Pat. No. 6,747,478.