« PreviousContinue »
(12) United States Patent
Schreiber et al.
(io) Patent No.: (45) Date of Patent:
US 7,363,459 B2 Apr. 22, 2008
(54) SYSTEM AND METHOD OF OPTIMIZING MEMORY USAGE WITH DATA LIFETIMES
(75) Inventors: Robert S. Schreiber, Palo Alto, CA (US); Alain Darte, Lyons (FR)
(73) Assignee: Hewlett-Packard Development
Company, L.P., Houston, TX (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 297 days.
(21) Appl. No.: 10/284,844
(22) Filed: Oct. 31, 2002
(65) Prior Publication Data
US 2004/0088515 Al May 6, 2004
(51) Int. CI.
(52) U.S. CI 711/202; 711/150; 711/170
(58) Field of Classification Search 711/202,
711/120, 150; 717/151, 152, 159, 160 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
U.S. Appl. No. 10/284,965, Gupta, et al.
R. Schreiber, et al. "PICO-NPA: High-Level Synthesis of
Nonprogrammable Hardware Accelerators," Journal of VLSI Signal
Processing, to appear.Hewlett-Packard Laboratories, Palo Alto,
California 94304-1126, pp. 1-22.
J. Steensma, et al., "Symbolic Macro Test for DSP Systems Applied
to a Voice Coder Application," pp. 215-223.
Christine Eisenbeis, et al., "A Strategy for Array Management in
Local Memory," (Jul. 1990), pp. 1-40.
A. Agarwal, et al., "Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared Memory Multiprocessors," pp. 1-41.
J. Rosseel, et al., "An Optimisation Methodology for Array Mapping of Affine Recurrence Equations in Video and Image Processing," IEEE, pp. 415-426 (1994).
S. Malik, "Analysis of Cyclic Combinational Circuits," Short
Papers IEEE Transactions on Computer-aided Design of Integrated
Circuits and Systems, vol. 13, No. 7, (Jul. 1994) pp. 950-956.
A. Srinivasan, et al. "Practical Analysis of Cyclic Combinational
Circuits," IEEE 1996 Custom Integrated Circuits Conference, pp.
Primary Examiner—Jack Lane
Guest Editorial, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 18, No. 1, (Jan. 1999) pp. 1-2. K. Danckaert, et al. "Strategy for Power-Efficient Design of Parallel Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 2, (Jun. 1999) pp. 258-265.
F. Vermeulen, et al., "Extended Design Reuse Trade-Offs in Hardware-Software Architecture Mapping," (2000) pp. 103-107.
R. Schreiber, et al., "High-Level Synthesis of Nonprogrammable
Hardware Accelerators," IEEE (2000) pp. 1-12.
S. Mahlke, et al., "Bitwidth Cognizant Architecture Synthesis of
Custom Hardware Accelerators," IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol. 20, No. 11,
(Nov. 2001) pp. 1355-1371.
P. R. Panda, et al., "Data and Memory Optimization Techniques for
Embedded Systems," ACM Transactions on Design Automation of
Electronic Systems, vol. 6, No. 2, (Apr. 2001) pp. 149-206.
S. Meftali, et al., "An Optimal Memory Allocation for Application-
Specific Multiprocessor System-on-Chip," (2001) pp. 19-24.
T. Van Achteren, et al., "Data Reuse Exploration Techniques for
Loop-dominated Applications," Proceedings of the 2002 Design,
Automation and Test in Europe Conference and Exhibition , IEEE
Computer Society, (Jan. 2002).
"Omega Project Source Release, version 1.2 (Aug. 2002)," [on-line]
[retrieved on : Jul. 16, 2002], Retrieved from: http://www.cs.umd.
edu/projects/omega/release-1.2.html, pp. 1-2.
Seeds for Tomorrow's World—IMECnology, [on-line] [Retrieved
on Jun. 12, 2002] Retrived from: http://www.Imec.be/.
G. Havas, et al. "Extended GCD and Hermite Normal Form Algorithms Via Lattice Basis Reduction," Experimental Mafhmatics, v. 7 (1998).
Eddy De Greef, Francky Catfhoor, and Hugo De Man, Memory Size Reduction Through Storage Order Optimization for Embedded
Parallel Multimedia Applications, Parallel Computing, 1997, 23(12):1811-1837, North-Holland, Amsterdam, Netherlands. Fabien, Quillere and Sanjay Rajopadhye, Optimizing Memory Usage in the Polyhedral Model, ACM Transactions on Programming Languages and Systems, 2000, 22(5)773-815, ACM Press, New York.
Vincent Lefebvre and Paul Feautrier, Automatic Storage Manage-
ment for Parallel Programs, Parallel Computing, 1998, 24(3-4):
649-671, North-Holland, Amsterdam, Netherlands.
Alain Darte, Robert Schreiber, and Gilles Villard, Lattice-Based
Memory Allocation, Proceedings of the 2003 International Confer-
ence on Compilers, Architectures, and Synthesis for Embedded
Systems, pp. 298-308, Oct. 2003, ACM PRESS, New York.
Panda, P R etal—"Efficient Utilization of Scratch-Pad Memory in
Embedded Processor Applications"—Mar. 17, 1007—pp. 7-11.
Kandemir, M et al—"Compiler-Directed Selection of Dynamic
Memory Layouts"—Apr. 25, 2001—pp. 219-224.
Gran, P et al—"APEX: Access Pattern Based Memory Architecture
Exploration"—Sep. 30, 2001—pp. 25-32.
Catthoor, F et al—"Hot Topic Session: How to Solve the Current Memory Access and Data Transfer Bottlenecks . . . "—Mar. 27, 2000—pp. 426-433.
Kandemir, M et al—Exploiting Scratch-Pad Memory Using
Presburger Formulas—Sep. 30, 2001—pp. 7-12.
McFarland, MC et al—"The Hogh-Level Synthesis of Digital
Systems"—Proc of the IEEE vol. 78 No. 1—Feb. 1, 1990—pp.
Park, N et al—Sehwa: A Software Package for Synthesis of Pipelines From Behavioral Specifications—IEEE Transactions vol. 7 No. 3—Mar. 1998—pp. 356-370.
* cited by examiner