United States Patent  [ii] Patent Number: 5,568,438
Penchuk  Date of Patent: Oct. 22, 1996
 SENSE AMPLIFIER WITH OFFSET AUTONULLING
 Inventor: Robert A. Penchuk, Wrentham, Mass.
 Assignee: Analog Devices, Inc., Norwood, Mass.
 Appl. No.: 503,529
 Filed: Jul. 18,1995
 Int. CI.6 G11C 7/00
 U.S. CI 365/208; 327/52; 327/54
 Field of Search 365/205, 207,
365/208, 203; 327/51, 52, 53, 54
 References Cited
U.S. PATENT DOCUMENTS
4,547,685 10/1985 Wong 365/208
4,724,344 2/1988 Watanabe 327/53
4,952,826 8/1990 Hoshi 365/205
4,973,864 11/1990 Nogami 365/205
5,473,567 12/1995 McClure 365/208
P. Gillingham et al, "High-Speed, High-Reliability Circuit
Design for Megabit DRAM", IEEE Journal of Solid State
Circuits, vol. 26, No. 8, Aug. 1991, pp. 1171-1175.
T. Sugibayashi et al, ISSCC95 Digest of Technical Papers,
Feb. 17, 1995, pp. 254-255.
T. Sugibayashi et al, ISSCC Slide Supplement, Feb. 1995, pp. 196-197.
Primary Examiner—David C. Nelms
Assistant Examiner—Son Mai
Attorney, Agent, or Firm—-Wolf, Greenfield & Sacks, PC.  ABSTRACT
A sense amplifier for determining the state of a memory cell of a random access memory includes first and second transistors connected in a differential amplifier configuration. The first and second transistors have control electrodes coupled to Bit and Bit B lines, respectively, for sensing a state of the memory cell. The sense amplifier further includes third and fourth transistors connected in a differential amplifier configuration. The differential amplifier configuration has an offset error and provides differential outputs for indicating the state of the memory cell during a read phase. The sense amplifier further includes first and second capacitors respectively coupled between the control electrodes of the third and fourth transistors and a reference potential, and a feedback circuit for coupling voltages representative of the offset error to the first and second capacitors during a nulling phase in which the Bit and Bit B lines are not being read. The first and third transistors may be connected in series or in parallel. Similarly, the second and fourth transistors may be connected in series or in parallel. By nulling offset error, the access time of the RAM is reduced.
17 Claims, 3 Drawing Sheets