Assignee: Stratus Computer, Inc., Marlboro,
 Appl. No.: 898,157
 Filed: Jun. 15,1992
 Int. CI.6 G06F 13/00; G06F 13/38
 U.S. CI 395/846; 364/DIG. 1;
364/242.34; 364/DIG. 2; 364/940; 364/942.79;
 Field of Search 395/275, 200,
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Primary Examiner—Thomas C. Lee
Assistant Examiner—D. Dinh
Attorney, Agent, or Firm—Lahive & Cockfield
A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces."
24 Claims, 6 Drawing Sheets