United States Patent   Patent Number: 4,670,871
Vaidya  Date of Patent: Jun. 2,1987
 RELIABLE SYNCHRONOUS INTER-NODE COMMUNICATION IN A SELF-ROUTING NETWORK
 Inventor: Avinash K. Vaidya, Naperville, 111.
 Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories, Murray Hill, N.J.
 Appl. No.: 749,500
 Filed: Jun. 27,1985
 Int. CI." H04Q 11/04
 U.S. CI 370/60; 370/94
 Field of Search 370/60, 94, 85, 58,
 References Cited
U.S. PATENT DOCUMENTS
4,314,367 2/1982 Bakka et al 370/60
4,433,411 2/1984 Gefroerer et al 370/94
4,472,801 9/1984 Huang 370/60
4,491,945 1/1985 Turner 370/60
4,550,397 10/1985 Turner et al 370/60
Primary Examiner—Douglas W. Olms
Assistant Examiner—Curtis Kuntz
Attorney, Agent, or Firm—John C. Moran
A communication method and packet switching net
work in which self-routing packets are communicated among stages of switching nodes via inter-stage links whereon data of the packets is transmitted in one direction and the packet clocking signals are transmitted in the other direction. Upon having the capability to accept a packet from one of the inter-stage links, a switch node transmits the packet clock signals to the upstream stage connect to that link indicating the present capacity to accept a packet. Furthermore, each switch node after receiving the end of a packet from an upstream stage times for a predefined amount of time before commencing the transmission of the packet clocking signals. That delay allows the transmitting switch node in the upstream stage to determine that the link and the downstream node are functioning correctly since continued transmission of the packet clock signals indicates that the packet had not been received or that downstream node had incorrectly responded to receipt of the packet. If a malfunction is detected, an error indication is transmitted to the computer controlling the switching network. Furthermore, upon receipt of a system reset signal, all switch nodes immediately transmit the packet clock signals to upstream stages; and the switch nodes in the upstream stages transmit the error indication if the packet clock signals are not received over a particular link within the predefined amount of time.
21 Claims, 9 Drawing Figures