(12) United States Patent ao) Patent No.: Us 7,178,001 B2
Mes (45) Date of Patent: *Feb. 13,2007
(54) SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
(75) Inventor: Ian Mes, Nepean (CA)
(73) Assignee: Mosaid Technologies Inc., Kanata (CA)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
This patent is subject to a terminal disclaimer.
(21) Appl. No.: 10/855,968
(22) Filed: May 28, 2004
(65) Prior Publication Data
US 2005/0033899 Al Feb. 10, 2005
Related U.S. Application Data
(63) Continuation of application No. 10/290,317, filed on Nov. 8, 2002, now Pat. No. 6,772,312, which is a continuation of application No. 09/129,878, filed on Aug. 6, 1998, now Pat. No. 6,539,454.
(30) Foreign Application Priority Data
Apr. 1, 1998 (CA) 2233789
(56) References Cited
U.S. PATENT DOCUMENTS 4,658,354 A 4/1987 Nukiyama
FOREIGN PATENT DOCUMENTS
EP 0 704 848 A2 4/1996
JP 09 091955 A 4/1997
Boerno, Lopez-Buedo and Meneses, "The Wave Pipeline Effect on LUT-based FPGA Architectures", Ciudad Universitaria, Madrid, Spain.
Primary Examiner—Reginald Bragdon
Assistant Examiner—Mehdi Namazi
(74) Attorney, Agent, or Firm—Shin Hung; Borden Ladner
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.
35 Claims, 18 Drawing Sheets