PHASE-LOCKED LOOP START-UP
Inventors: David H. Shen, San Jose, CA (US); Ann
P. Shen, Saratoga, CA (US); Axel
Schuur, Mountain View, CA (US)
Assignee: NanoAmp Mobile, Inc., Santa Clara,
Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 132 days.
Filed: Apr. 25, 2008
Prior Publication Data
US 2009/0085622 Al Apr. 2, 2009
Related U.S. Application Data
Provisional application No. 60/975,733, filed on Sep. 27, 2007.
H03L 7/10 (2006.01)
H03L 7/18 (2006.01)
H04B 1/00 (2006.01)
U.S. CI 331/16; 331/18; 331/25;
Field of Classification Search 331/1 A,
331/4, 8, 14, 16-18, 25, DIG. 2; 327/156-159;
332/127; 360/51; 375/376; 455/260 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,068,625 A 11/1991 Baker et al.
5,193,005 A 3/1993 Tomita
Implementations feature systems and techniques for phaselocked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
29 Claims, 5 Drawing Sheets