United States Patent  [H] Patent Number: 5,594,702
Wakeman et al.  Date of Patent: Jan. 14, 1997
 MULTI-FIRST-IN-FIRST-OUT MEMORY CIRCUIT
 Inventors: Larry N. Wakeman, Mountain View;
Roy T. Myers, Jr., Santa Clara; Wesley
C. Lee, San Jose, all of Calif.
 Assignee: National Semiconductor Corporation,
Santa Clara, Calif.
 Appl. No.: 495,867
 Filed: Jim. 28, 1995
 Int. CI.6 G11C 8/00; G06F 15/00;
 U.S. CI 365/230.05; 365/230.08;
365/230.09; 365/239; 395/501; 395/507;
 Field of Search 365/230.05, 230.08,
365/230.09, 239; 395/162, 164, 166, 275
 References Cited
U.S. PATENT DOCUMENTS
5,333,274 7/1994 Amini et al 395/275
5,353,403 10/1994 Kohiyama et al 395/164
International Standard ISO/IEC 8802-3:1992 (Information Technology—Local and Metropolitan Area Networks—Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA /CD) Access Method and Physical Layer Specifications), Third Edition, The Institute of Electrical and Electronic Engineers, Inc., 1992, pp. 31-41, 43-47, 49-78, 81-119, and 121-149.
A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators. Each pair of pointer registers includes a read pointer register that indicates a corresponding group's next storage element to be read and a write pointer register that indicates the group's next storage element to be written.
9 Claims, 10 Drawing Sheets