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US007301820B2

(12;

United States Patent

Ogura et al.

(io) Patent No.: (45) Date of Patent:

US 7,301,820 B2 Nov. 27, 2007

(54) NON-VOLATILE MEMORY DYNAMIC OPERATIONS

(75) Inventors: Seiki Ogura, Hillsboro, OR (US); Nori Ogura, Hillsboro, OR (US)

(73) Assignee: Halo LSI, Inc., Hillsboro, OR (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 11/124,220

(22) Filed: May 6, 2005

(65) Prior Publication Data

US 2005/0254305 Al Nov. 17, 2005

Related U.S. Application Data

(60) Provisional application No. 60/568,632, filed on May 6, 2004.

(51) Int. CI.

G11C11/34 (2006.01)
G11C16/04 (2006.01)

(52) U.S. CI 365/185.26; 365/185.19;

365/185.28; 365/185.06

(58) Field of Classification Search 365/185

See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

5,587,947 A * 12/1996 Chang et al 365/185.3

6,108,239 A * 8/2000 Sekariapuram et al. 365/185.28

6,114,724 A * 9/2000 Ratnakumar 257/326

6,255,166 Bl 7/2001 Ogura et al 438/257

6,459,622 Bl * 10/2002 Ogura et al 365/185.28

6,549,463 B2 * 4/2003 Ogura et al 365/185.18

6,873,550 B2* 3/2005 Mihnea 365/185.19

6,898,126 Bl * 5/2005 Yang et al 365/185.26

OTHER PUBLICATIONS

Ogura, et al. "Twin MONOS: a nitride based dual bit flash memory", Nov. 15-17, 2004, Non-Volatile Memory Technology Symposium, 2004, 157-160 *

Ogura, et al. "Twin MONOS cell with dual control gates", Jun. 13-15, 2000, Symposium on VLSI Technology, 2000, 122-123.* Tatsuya Ishii, et al., "A 126.6 mm2 AND-type 512 M6 Flash Memory with 1.8V Power Supply" ISSCC 2001.

* cited by examiner

Primary Examiner—Amir Zarabian

Assistant Examiner—Michael Weinberg

(74) Attorney, Agent, or Firm—Saile Ackerman LLC;

Stephen B. Ackerman

(57) ABSTRACT

A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched such that one or more of the source side sub bit line or the drain side sub bit line is floating when all other program voltages are applied to a selected cell.

11 Claims, 6 Drawing Sheets

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FIG. 2 Prior Art

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FIG. 3 Prior Art

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