Automated processor generation system for designing a configurable processor ...

AUTOMATED PROCESSOR GENERATION SYSTEM FOR DESIGNING A CONFIGURABLE PROCESSOR AND METHOD FOR THE SAME

Inventors: Earl A. Killian, Los Altos Hills, CA
(US); Ricardo E. Gonzalez, Menlo
Park, CA (U S); Ashish B. Dixit,
Mountain View, CA (U S); Monica Lam,
Menlo Park, CA (U S); Walter D.
Lichtenstein, Belmont, MA (U S);
Christopher Rowen, Santa Cruz, CA
(US); John C. Ruttenberg, Newton,
MA (US); Robert P. Wilson, Palo Alto,
CA (U S); Albert Ren-Rui Wang,
Fremont, CA (US); Dror Eliezer
Maydan, Palo Alto, CA (US)

Assignee: Tensilica, Inc., Santa Clara, CA (U S)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. l54(b) by 31 days.

This patent is subject to a tenninal disclaimer. Appl.No.: 11/391,773 Filed: Mar. 27, 2006

Prior Publication Data US 2006/0259878 A1 Nov. 16, 2006

Related U.S. Application Data

Continuation of application No. 10/884,590, filed on Jul. 2, 2004, now Pat. No. 7,020,854, which is a continuation of application No. 10/286,496, filed on Nov. 1, 2002, now Pat. No. 6,760,888, which is a continuation of application No. 09/246,047, filed on Feb. 5, 1999, now Pat. No. 6,477,683.

Int. Cl.
G06F 17/50 (2006.01)

(52) U.S. Cl. ...... .. 716/100; 716/116; 716/117; 716/132; 716/133; 716/139; 700/1; 700/200; 700/220;

717/124; 717/139; 717/140

(58) Field of Classification Search ........ .. 716/1, 16-17, 716/100,116,117,132,133,139; 712/1,

712/200, 220; 717/124, 139, 140

See application file for complete search history.

(56) References Cited U.S. PATENT DOCUMENTS 5,450,586 A 9/1995 Kuzara et al. ................... .. 717/4 (Continued)

FOREIGN PATENT DOCUMENTS EP 0 743 599 11/1996 (Continued)

OTHER PUBLICATIONS

Freericks, “The nML Machine Description Formalism” (Bericht 1991/15 pp. 3-41).

(Continued)

Primary Examiner — Thuan D0

Assistant Examiner — Nha T Nguyen

(74) Attorney, Agent, or Firm — PillsbLu"y Winthrop Shaw Pittman LLP

(57) ABSTRACT

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

19 Claims, 14 Drawing Sheets

U.S. PATENT DOCUMENTS

5,535,331 A 7/1996 Swobodaetal. ............. .. 714/45 5,563,987 A * 10/1996 Scott ......... .. 358/1.16 5,748,875 A 5/1998 Tzori ........ .. 714/29 5,781,763 A * 7/1998 Beukema et al 710/22 5,819,050 A 10/1998 Boehling et al. 710/104 5,854,929 A 12/1998 Van Praet etal. 717/5 5,867,399 A * 2/1999 Rostokeret al. 716/18 5,867,400 A * 2/1999 El-Ghoroury et al. 716/1 5,870,588 A 2/1999 Rompaey et al. 703/13 5,896,521 A * 4/1999 Shackleford et al. 703/21 5,918,035 A 6/1999 Van Praet et al. ........... .. 395/500 5,964,861 A 10/1999 Gabzdyletal.

5,999,734 A 12/1999 Willis et al. ..................... .. 717/6 6,006,022 A 12/1999 Rhim et al. ..................... .. 716/1 6,052,518 A 4/2000 Shigeta et al.

6,101,592 A * 8/2000 Pechanek et al. ............. .. 712/20
6,115,034 A * 9/2000 Tanaka et al. . 715/700
6,148,374 A * 11/2000 Pawlowski 711/128
6,166,728 A * 12/2000 Hamanet al. 715/719
6,182,206 B1 1/2001 Baxter 712/43
6,195,593 B1 2/2001 Nguyen 700/97
6,477,683 B1 11/2002 Killian et al. ................... .. 716/1
6,618,854 B1* 9/2003 Mann .......................... .. 717/124
6,839,889 B2 1/2005 Liu ............................... .. 716/18

FOREIGN PATENT DOCUMENTS
JP 10-187484 7/1998
WO WO 99/00731 1/1999
OTHER PUBLICATIONS

Fauth et al. Describing instruction set processors using nML (Proc. Euro. Design & Test Conf. Paris Mar. 1995, IEEE 1995, 5 pp.). Hadjiyiannis et al. “ISDL: an instruction set description language for retargetability” DAC ’97, Anaheim California, 1997 ACM 0-89791920-3/97/06.

Leupers et al. “Retargetable Code Generation Based on Structural Processor Descriptions” (Design Automation for Embedded Systems, vol. 3, No. 1, Jan. 1998, pp. 1-36.

Zivojnovic et al. “DSP Processor/Compiler Co-Design: a quantitative approach” (9’h Int’l Symposium on System Synthesis (ISSS ’96), Nov. 6-8, 1996, San Diego, CA.

Fauth et al., “Generation of hardware machine models from instruction set descriptions,”VLSI Signal ProcessingVI, 1993,Workshop on Veldhoven, Netherlands, 20-22, Oct. 1993, New York NY, USA, IEEE Oct. 20, 1993 pp. 242-250.

Hartoog et al. “Generation of Software Tools from Processor Descriptions for Hardware/ Software Codesign” (ACM, Jun. 1997, pp. 303-306.

Internet Publication http://www.retarget.com/brfchschk.htn1l (19 pp. undated).

Internet Publication http://www.synopsys.com/products/ designware/8051 ds.htn1l (8pp. undated).

Internet Publication http://www.synopsys.com/oruducts/ designware/dwpci_ds.html (16 pp. undated).

Internet Publication http1//www.lexra.com/product.html (11 pp. undated).

Internet Publication http://www.risccorescom/html/body_ aboutarc.htm (13 pp. undated).

Tensilica “Xtensa” Instruction Set Architecture (ISA) Ref. Manual. Rev. 1.0, Tensilica, Inc.

Fauth, A., et al., “Describing Instruction Set Processors Using nML,” IEEE, p. 503-507, (1995).

Hartoog, Mark R., et al., “Generation of Software Tools from Processor Descriptions for Hardware/ Software Co-design,” 34th Design Automation Conference (DAC), p. 1-4, (1997).

Akaboshi, et al., “Study on Design Support for Computer Architecture”, Design Automation, 68-7, 13 pages (Oct. 28, 1993).

Fauth, et al., “Describing Instruction Set Processors Using nML”, Proc. EP Design and Test Conf, Parish, Mar. 1995, 5 pages. Hadjiyiannis, G., et al., “ISDL: An Instruction Set Description Language for Retargetability”, Jun. 9, 1997, 4 pages.

Hakata, et al., “A Software Development Took Generator for ASIC CPU”, Design Automation, 62-25, May 18, 1992, pp. 144- 147. Hikichi, et al.,, “Compilers for Embedded System”, Tech. Report of IEICE, Apr. 1998, 13 pages.

Ohtsuki, et al., “HW/SW Co-Design System PEAS-II for VLIW Processor”, DA Symposium, Jul. 1998, 7 pages.

Sato, et al., “Implementation and Evaluation of PEAS: Practical Environment for ASIP Development”, Design Automation, 64-11, Oct. 23, 1992, pp. 79-86.

Shiomi, et al., “Proposal of Co-Design Workbench PEAS-III for ASIP Design”, Design Automation, 76-10, Jul. 20, 1995, pp. 73-80. Clucas, R., “Designing with a Customisable Microprocessor Core”, Electronic Engineering, vol. 71, No. 865, Feb. 1, 1999, p. 35. Nurprasetyo, et al., “Soft-Core Processor Architecture for Embedded System Design”, IEICE Trans. on Electronics, Electronics Soc., vol. E81-C, No. 9, Sep. 1, 1998, pp. 1416-1423.

Sato, et al., “PEAS-1: A hardware/Software Codesign System for ASIP Development”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Engineering Sciences Soc., vol. E77-A, No. 3, Mar. 1, 1994, pp. 483-491.

Shackleford, et al., “Satsuki: An Integrated Processor Synthesis and Compiler Generation System”, IEICE Trans. on Information and Systems, Information and Society; vol. E79-D, No. 10, Oct. 1, 1996, pp. 1373-1381.

Yang, et al., “MetaCore: An Application specific DSP Development System”, Design Automation Conf., 1998, Proc. San Francisco, CA , Jun. 15-19, 1998, IEEE, Jun. 15, 1998, pp. 800-803.

* cited by examiner