(54) SOLID-STATE IMAGING DEVICE, METHOD OF DRIVING SOLID-STATE IMAGING DEVICE, CAMERA DEVICE, AND CAMERA SYSTEM
(75) Inventor: Tomio Ishigami, Kanagawa (JP)
(73) Assignee: Sony Corporation, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 08/916,038
(22) Filed: Aug. 21, 1997
Related U.S. Application Data
(63) Continuation of application No. PCT/JP96/03609, filed on Dec. 11, 1996.
(30) Foreign Application Priority Data
Dec. 21, 1995 (JP) 7-333644
(51) Int. CI.7 H04N 3/14
(52) U.S. CI 348/273
(58) Field of Search 348/312, 315,
348/316, 319, 320, 321, 322, 323, 273
(56) References Cited
U.S. PATENT DOCUMENTS
4,054,915 * 10/1977 Sugihara 348/322
4,740,828 * 4/1988 Kinoshita 348/322
4,805,026 * 2/1989 Oda 348/320
4,851,917 7/1989 Ohzu .
4,903,121 2/1990 Uomori et al. .
5.410,349 4/1995 Tanigawa et al. .
5,528,292 * 6/1996 Ikeda 348/273
5,956,086 * 9/1999 Sawanobori 348/273
An all-pixel reading image sensor or a noninterlaced output image sensor, in which an interlaced signal can selectively be output without the use of a frame memory or the like as an external circuit. For outputting an interlaced signal from a three-layer three-phase drive all-pixel reading CCD image sensor, vertical shift registers are supplied with first through third vertical transfer pulses to transfer signal charges in the pixels of an nth line, for example, to a horizontal shift register, and then the horizontal shift register is supplied with horizontal transfer pulses to transfer (shift) the signal charges of the nth line stored in the horizontal shift register by two pixels, for example, to an output unit. Thereafter, the vertical shift registers are supplied with first through third vertical transfer pulses to transfer signal charges in the pixels of an (n+l)th line to the horizontal shift register, in which the signal charges of the nth line and the signal charges of the (n+l)th line are mixed with each other.
22 Claims, 14 Drawing Sheets