DESIGN FOR A SIMULATION MODULE USING AN OBJECT-ORIENTED PROGRAMMING LANGUAGE
 Inventor: Warren G. Stapleton, San Jose, Calif.
 Assignee: Advanced Micro Devices, Inc., Austin, Tex.
 Appl. No.: 592,041
 Filed: Jan. 26, 1996
Related U.S. Application Data
 Provisional application No. 60/005,045 Oct. 10, 1995.
 Int. CI. G06F 9/455
 U.S. CI 395/500
 Field of Search 395/500; 364/578,
364/488, 489, 490, 491, 483
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Primary Examiner—Kevin J. Teska
Assistant Examiner—Dan Fiul
Attorney, Agent, or Firm—Skjerven, Morrill, MacPherson,
Franklin & Friel LLP; Edward C. Kwok
A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.
14 Claims, 4 Drawing Sheets