(12) United States Patent (io> Patent No.: us 6,598,154 Bi
Vaid et al. (45) Date of Patent: Jul. 22,2003
(54) PRECODING BRANCH INSTRUCTIONS TO REDUCE BRANCH-PENALTY IN PIPELINED PROCESSORS
(75) Inventors: Kushagra Vaid, Sunnyvale, CA (US);
Frederick R. Gruner, Palo Alto, CA
(US)
(73) Assignee: Intel Corporation, Santa Clara, CA
(US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/223,079
(22) Filed: Dec. 29, 1998
(51) Int. CI. G06F 9/38
(52) U.S. CI 712/237; 712/210; 712/213
(58) Field of Search 712/233-235,
712/237-240
(56) References Cited
U.S. PATENT DOCUMENTS
5,381,532 A * 1/1995 Suzuki 712/237
5,513,330 A * 4/1996 Stiles 712/204
A method of reducing the branch penalty in a microprocessor includes predecoding the instruction to determine whether an instruction is a branch, the length of the instruction, and prediction marker information for the instruction should it be a branch. The target of the branch is relayed to the align stage of the microprocessor to readjust the read pointer to point to the target of the branch if the instruction is a branch. An apparatus for reducing the branch penalty in a microprocessor includes a branch predecode and taken resolution unit which determines whether an instruction is a predicted taken branch, and relays that information to the align stage of the microprocessor to deliver the target of the branch to the align stage as early as possible.
30 Claims, 4 Drawing Sheets
