High-performance fault tolerant computer system with clock length ...

United States Patent [w]

Vrba et al.

US005845060A [ii] Patent Number: [45] Date of Patent:

5,845,060 *Dec. 1, 1998

[54] HIGH-PERFORMANCE FAULT TOLERANT COMPUTER SYSTEM WITH CLOCK LENGTH SYNCHRONIZATION OF LOOSELY COUPLED PROCESSORS

[75] Inventors: Richard Alan Vrba; James Stevens

Klecka, both of Austin; Kyran Wilfred
Fey, Jr., Pfiugerville; Larry Leonard
Lamano; Nikhil A. Mehta, both of
Austin, all of Tex.

[73] Assignee: Tandem Computers, Incorporated,

Cupertino, Calif.

[ * ] Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions of 35 U.S.C. 154(a)(2).

[21] Appl. No.: 642,798
[22] Filed: May 2, 1996

Related U.S. Application Data

[63] Continuation of Ser. No. 25,283, Mar. 2, 1993, abandoned.

[51] Int. CI.6 G06F 1/12; G06F 13/42

[52] U.S. CI 395/182.1; 395/200.78;

395/553; 375/356

[58] Field of Search 395/182.1, 182.08,

395/182.11, 550, 182.09, 200.78, 551, 552, 553, 556, 558; 364/268.9, 269, 269.1, 931.48, 271; 375/354, 355, 356, 357

[56] References Cited

U.S. PATENT DOCUMENTS

4,589,066 5/1986 Lam et al 364/200

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

29 Claims, 17 Drawing Sheets