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United States Patent
(io) Patent No.: (45) Date of Patent:
US 7,879,738 B2 Feb. 1, 2011
(54) CHARGE TRAPPING DIELECTRIC STRUCTURE FOR NON-VOLATILE MEMORY
(75) Inventor: Szu Yu Wang, Kaoshing (TW)
(73) Assignee: Macronix International Co., Ltd.,
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 387 days.
(21) Appl.No.: 11/466,079
(22) Filed: Aug. 21, 2006
(65) Prior Publication Data
US 2006/0281331 Al Dec. 14, 2006
Related U.S. Application Data
(62) Division of application No. 10/998,445, filed on Nov. 29, 2004, now abandoned.
(51) Int. CI.
H01L 21/469 (2006.01)
(52) U.S. CI 438/778; 438/90; 257/E29.309;
(58) Field of Classification Search 257/640,
257/649, 324, 316, 325, 639, 410, 321; 438/261,
See application file for complete search history. (56) References Cited
U.S. PATENT DOCUMENTS
An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage.
4 Claims, 5 Drawing Sheets
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