United States Patent  [H] Patent Number: 5,138,411
Sandhu  Date of Patent: Aug. 11, 1992
 ANODIZED POLYSILICON LAYER LOWER CAPACITOR PLATE OF A DRAM TO INCREASE CAPACITANCE
 Inventor: Gurtej S. Sandhu, Boise, Id.
 Assignee: Micron Technology, Inc., Boise, Id.
 Appl. No.: 696,446
 Filed: May 6,1991
 Int. CI.* H01L 27/108
 U.S. CI 357/23.6; 357/59
 Field of Search 357/23.6, 59, 51
 References Cited
U.S. PATENT DOCUMENTS
4,057,823 11/1977 Burkhardt et al 357/52
4,801,380 1/1989 Parker et al 264/45.6
5,043,780 8/1991 Fazan et al 357/23.6
5,068,199 11/1991 Sandhu 357/23.6
M. I. J. Beale, N. G. Chew, M. J. Uren, A. G. Cullis, and J. D. Benjamin; "Microstructure and Formation Mechanism of Porous Silicon"; Jan. 1, 1985, Appl. Phys. Lett., pp. 86-88.
Primary Examiner—William D. Larkins
A DRAM cell having enhanced-capacitance attributable to the use of a textured structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated depressions in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated depressions in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.
41 Claims, 10 Drawing Sheets