(12) United States Patent ao) Patent No.: us 6,187,678 Bi
Gaynes et al. (45) Date of Patent: Feb. 13,2001
(54) HIGH DENSITY INTEGRATED CIRCUIT PACKAGING WITH CHIP STACKING AND VIA INTERCONNECTIONS
(75) Inventors: Michael Anthony Gaynes, Vestal, NY (US); Alan James Emerick, Warren Center, PA (US); Viswanadham Puligandla, Lewisville, TX (US); Charles Gerard Woychik, Vestal, NY (US); Jerzy Maria Zalesinski, Essex Junction, VT (US)
(73) Assignee: International Business Machines Corporation, Armonk, NY (US)
( * ) Notice: Under 35 U.S.C. 154(b), the term of this patent shall be extended for 0 days.
(21) Appl. No.: 09/379,716
(22) Filed: Aug. 24, 1999
Related U.S. Application Data
(62) Division of application No. 08/578,922, filed on Dec. 27, 1995, now Pat. No. 6,002,177.
(51) Int. C I. H01L 21/44
(52) U.S. CI 438/667; 438/559; 438/624
(58) Field of Search 438/667, 479,
438/624, 462, 439, 460, 559; 156/643, 656; 216/13, 95; 437/208, 686
(56) References Cited
U.S. PATENT DOCUMENTS
3,615,943 * 10/1971 Genser 438/559
4,348,253 * 9/1982 Subbarao et al 156/643
4,394,712 7/1983 Anthony 361/779
4,437,109 3/1984 Anthony et al 257/507
4,499,655 2/1985 Anthony 438/109
4,754,316 6/1988 Reid 257/777
4,761,681 * 8/1988 Reid 357/68
Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.