United States Patent m
Shen et al.
US005659721A [li] Patent Number:  Date of Patent:
 PROCESSOR STRUCTURE AND METHOD FOR CHECKPOINTING INSTRUCTIONS TO MAINTAIN PRECISE STATE
 Inventors: Gene W. Shen, Mountain View; John Szeto, Oakland; Niteen A. Patkar, Sunnyvale, all of Calif.; Michael C. Shebanow, Piano, Tex.
 Assignee: HAL Computer Systems, Inc.,
 Appl. No.: 476,419
 Filed: Jun. 7,1995
Related U.S. Application Data
 Continuation of Ser. No. 398,299, Mar. 3,1995, abandoned, which is a continuation of Ser. No. 390,885, Feb. 14,1995, abandoned.
 Int CI.6 G06F 11/00
 U.S. CI 395/569; 395/800.23
 Field of Search 395/375, 800
 References Cited
U.S. PATENT DOCUMENTS
5,313,647 5/1994 Kaufman et al. .
5,355,457 10/1994 Shebanow et al 395/375
5,463,745 10/1995 Vidwans et al 395/375
5,471,598 11/1995 Quattromani et al 395/375
5,479,622 12/1995 Grohoski et al 395/375
5,481,685 1/1996 Nguyen et al 395/375
5,497,499 3/1996 Garg et al 395/375
5,511,172 4/1996 Kimuraetal 395/375
Hwu et al., "Checkpoint Repair for High-Performance Out-of-Order Execution Machines", IEEE Transactions on Computers, vol. C-36, No. 12, Dec. 1987, pp. 1496-1514. Mike Johnson, Superscalar Microprocessor Design, 1991.
Primary Examiner—William M. Treat
Attorney, Agent, or Firm—Flebi Hohbach Test Albritton &
Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-cut conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional, checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
50 Claims, 60 Drawing Sheets
f START 1
I REDUCED STORAGE CHECKPOINTING I
PRE-IDENTIFY INSTRUCTIONS FROM AMONG THE
SET OF INSTRUCTIONS SUPPORTED BY THE
PROCESSOR (e.g. CPU INSTRUCTION SET) THAT MAY
MODIFY PROCESSOR STATE DURING EXECUTION.
Pk-seuct k Pariicujw First Et Of Bsiheiios noi is m-z&vnB
INSTRUCTIONS THAT MAY MODIFY PROCESSOR STATE FOR EXECUTION IN A SPECIAL EXECUTION MODE (i.e. STCHROtJIZED MODE) WITHOUT CHECKPOINTING , THE SELECTED INSTRUCTION PRIOR TO EXECUTION J3A5ED ON CRITERIA INCLUDING THE TYPE AND AMOUNT OF UCOIFYABLE STATE.
PRE-SELECT ANOTHER SECOND SET OF THE PRE-IDEHTIFIED
INSTRUCTIONS FOR CHECKPOINTING PROCESSOR
STATE PRIOR TO EXECUTION BASED ON CRITERIA INCLUDING
THE TYPE AND AMOUNT OF MODIFYABLE STATE
OPTIONALLY: FORMING A CHECKPOINT FOR
ANY ISSUED INSTRUCTION OTHER THAN ONE
OF THE FIRST SET BASED ON THE INTERVAL
SINCE THE LAST CHECKPOINT (TIME-OUT CHECKPOINT}
EXECUTE INSTRUCTIONS IN THE
PROCESSOR ACCORDING TO THE