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United States Patent
Lung et al.
(io) Patent No.: (45) Date of Patent:
US 7,579,613 B2 Aug. 25, 2009
FOREIGN PATENT DOCUMENTS
WO WO-00/79539 12/2000
Hwang, Y. N. et al., "Full Integration and Reliability Evaluation of Phase-Change RAM Based on 0.24 urn-CMOS Technologies," 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 173-174.
(Continued) Primary Examiner—Mark Prenty
(74) Attorney, Agent, or Firm—Haynes Beffel & Wolfeld LLP
A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an interelectrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.
11 Claims, 53 Drawing Sheets
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