[54] METHOD AND SYSTEM FOR OPTIMIZING A CRITICAL PATH IN A FIELD PROGRAMMABLE GATE ARRAY CONFIGURATION
[75] Inventors: Christine Marie Fuller, Williston;
Steven Paul Hartman, Jericho; Eric
Ernest Millham. St. George, all of Vt.
[73] Assignee: International Business Machines
Corporation, Armonk, N.Y.
[21] Appl. No.: 518,515
[22] Filed: Aug. 23, 1995
[51] IntCL6 G06F 9/455
[52] U.S. CI 395/500; 364/491; 364/488
[58] Field of Search 395/500; 364/488,
364/489, 490. 491
[56] References Cited
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Primary Examiner—-Kevin J. Teska
Assistant Examiner—Matthew Clay Loppnow
Attorney, Agent, or Firm—Heslin & Rothenberg. P.C.
[57] ABSTRACT
In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.
9 Claims, 3 Drawing Sheets
