United States Patent m
Orsino et al.
 METHOD AND APPARATUS FOR
COMPUTING ARITHMETIC EXPRESSIONS
USING ON-LINE OPERANDS AND
 Inventors: Francesco Orsino. North Babylon;
Chung-Tao D. Wang. Melville, both of N.Y.
 Assignee: AIL Systems, Inc., Deer Park. N.Y.  Appl. No.: 664.525  Filed: Mar. 5, 1991
Related U.S. Application Data
 Continuation of Ser. No. 45S.778. Dec. 29. 1989. abandoned.
 Int. Cl.f G06F7/38
 U.S. CI 364/736: 364/759
 Field of Search 364/754. 759. 760. 736.
 References Cited
U.S. PATENT DOCUMENTS
4.575.812 3/1986 Kloker et al 364/760
4.514.678 6/1986 Uhlenhoff 364/736
4.638.449 1/1987 Frey 364/760
4.852.037 7/1989 Aoki 364/736
4.890.127 12/1989 Darley 364/786
Design and VLSI Implementation Of An On-Line Al-
gorithm, by D. Ercegovac. et al.. vol. 698 Real Time
Signal Processing IX (1986). Society of Photo Optical
Instrumentation Engineers (SPIE). p. 92.
A General Method For Evaluation Of Functions And
Computations In A Digital Computer, by Milos Dragu-
[ii] Patent Number: 5,113,363  Date of Patent: May 12, 1992
tin Ercegovac. Jul.. 1975. Library of the University of Illinois. Microfilm No. 76-6758.
Primary Examiner—Gary V. Harkcom
Assistant Examiner—Tan V. Mai
Attorney. Agent, or Firm—Hoffmann & Baron
Method and apparatus for processing on-line operands A, B and C to produce the arithmetic expression S = (AxB)+C. In general, the apparatus includes an input processing unit, an on-line multiplication unit, and an on-line serial addition unit. The input processing unit is sequentially introducing the digits of operands. A, B and C into the apparatus, where each digit is represented in a redundant binary number format. The multiplication unit multiplies the sequence of digits of the operands A and B to produce the n-th product digit p„ of the product P = A X B. with the most significant digit p0 being computed first. The on-line addition unit adds the n-th product digit to the n-th digit of on-line operand C, so as to produce the n-th digit s„of the arithmetic expression S = (AxB) + C, with the most significant digit s0 being produced first. In one embodiment, the input processing unit includes a selective conversion subunit for selectively converting the digits of operands A. B and C sequentially entering the computational device, so that each digit is represented in a redundant number format. In such an embodiment, the redundant binary number format is characterized by signed digit numbers, and the selective conversion subunit includes a binary-to-signed digit converter.
8 Claims, 10 Drawing Sheets