(12) United States Patent ao) Patent No.: Us 7,563,629 B2
Lee et al. (45) Date of Patent: Jul. 21,2009
(54) METHOD OF FABRICATING VERTICAL STRUCTURE LEDS
(75) Inventors: Jong-Lam Lee, Kyungbuk (KR);
In-Kwon Jeong, Cupertino, CA (US);
Myung Cheol Yoo, Pleasanton, CA (US)
(73) Assignee: LG Electronics Inc., Seoul (KR)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 97 days.
(21) Appl.No.: 11/232,957
(22) Filed: Sep. 23, 2005
(65) Prior Publication Data
US 2006/0099730 Al May 11, 2006
Related U.S. Application Data
(62) Division of application No. 11/002,413, filed on Dec. 3,2004, which is a division of application No. 10/118, 316, filed on Apr. 9, 2002, now abandoned.
(51) Int. CI.
H01L 51/56 (2006.01)
H01L 27/15 (2006.01)
(52) U.S. CI 438/34; 438/38; 438/42;
438/46; 438/47; 438/458; 438/459; 438/958; 438/977; 257/E33.025; 257/E33.028; 257/E21.053
(58) Field of Classification Search 438/459,
438/977, 22, 455, 458, 405, 34, 38, 42, 46, 438/47, 958; 257/E33.025, E33.028, E33.046, 257/E33.048, E21.053 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
3,602,982 A * 9/1971 Kooi 438/396
A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
41 Claims, 7 Drawing Sheets