(54) OUTPUT CIRCUIT OF A MEMORY AND METHOD THEREOF
(75) Inventor: Chao-Sheng Huang, Taipei (TW)
(73) Assignee: Via Technologies, Inc., Taipei (TW)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 111 days.
(21) Appl. No.: 11/385,535
(22) Filed: Mar. 20, 2006
(65) Prior Publication Data
US 2007/0115739 Al May 24, 2007
(30) Foreign Application Priority Data
Nov. 24, 2005 (TW) 94141260 A
(51) Int. CI.
G11C 8/00 (2006.01)
G11C 7/02 (2006.01)
(52) U.S. CI 365/230.05; 365/207
(58) Field of Classification Search 365/230.05,
365/207, 203, 154 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
6,046,942 A * 4/2000 Hwang et al 365/189.05
6,181,634 Bl 1/2001 Okita
6,222,777 Bl * 4/2001 Khieu 365/189.02
6,317,379 Bl* 11/2001 Argyres 365/230.05
6,665,215 B2 12/2003 Thomas et al.
2005/0180197 Al * 8/2005 Huang 365/154
FOREIGN PATENT DOCUMENTS
JP 2000215674 A 8/2000
TW 1226638 1/2005
TW 1240277 9/2005
TW Office Action mailed Jul. 23, 2007.
* cited by examiner
Primary Examiner—Anh Phung
(74) Attorney, Agent, or Firm—Thomas, Kayden, Horstemeyer & Risley
An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a target memory cell is read to the read bit line, wherein the target memory cell is one of the plurality of memory cells, and a sense amplifier, coupled to the read bit line, detecting the voltage of the read bit line after the stored bit of the target memory cell is read to the read bit line, and comparing the voltage of the read bit line with the logic high level to respectively generate a comparison result signal and an inverse comparison result signal to a first output node and a second output node.
21 Claims, 4 Drawing Sheets