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U.S. PATENT DOCUMENTS 7,220,657 B2 5/2007 Ihara A /512/212 3% 2/522119.198 5,631,499 A 5/1997 Hosomi 7,405,149 B1 * 7/2008 Lin it al. ..................... .. 438/622 5,656,858 A 8/1997 Kondo et al. ............... .. 257/737 7’456’089 B2 U/2008 Aiba 5,656,863 A 8/1997 Yasunaga 7’462’942 B2 12/2008 Tan 5,664,642 A 9/1997 Williams ’ ’

2001/0040290 A1 11/2001 Sakura1

5,729,896 A 3/1998 Dalal et al. .................... .. 29/840 2002/0043723 A1 4/2002 Sh- 5,736,791 A 4/1998 Fujiki 2002/0127836 A1 * 9/2002 Lirllrgtzdl 438/612 ggggggg A 21332 iakrrnwortthl 438/51 2003/0006062 A1 1/2003 Stone 5,767,010 A 6/1998 M. me A """"""""""" " 2003/0111711 Al* 6/2003 Linetal. ..................... .. 257/635 5,854,513 A 12/1998 K.“ 2003/0133055 Al* 7/2003 Um etal. .. 349/43 5,877,078 A 3/1999 Ylm .da 2003/0137058 A1 * 7/2003 Magerlein etal. .......... .. 257/784 5,883,435 A 3/1999 Ganfgfl 2003/0218246 A1 11/2003 Abe 5,892,273 A 4/1999 I e E‘ 2004/0007779 A1 1/2004 Arbuthnot 5,898,222 A 4/1999 Fwas 1 2004/0070086 A1 * 4/2004 Lee etal. .................... .. 257/784 5903343 A 5/1999 Nigfgoq 2004/0126927 A1 * 7/2004 Lin et al. ..................... .. 438/107 539433597 A 8/ 1999 Kleffner FOREIGN PATENT DOCUMENTS 5,946,590 A 8/1999 Satoh JP 60217646 10/1985 5,985,765 A 11/1999 H ' 6,013,571 A 1/2000 M23211 JP 62160744 7/ 1987 6,028,363 A 2/2000 Lin JP 1061038 3/1989 6,042,953 A 3/2000 Yamaguchi JP 03022437 1/ 1991 6,075,290 A 6/2000 Schaefer JP 4278543 10/1992 6,077,726 A 6/2000 Mistry E 3312?; 15332 6,093,964 A 7/2000 Saitoh 6,144,100 A 11/2000 Shen JP 10107064 4/1998 6,144,102 A 11/2000 Amagai JP 2000260803 9/2000 6,162,652 A 12/2000 Dass JP 2002016096 1/2002 6,180,265 B1 1/2001 Erickson JP 2003133477 5/2003 6,187,680 B1 2/2001 Costrini JP 2003234367 8/2003 6,194,309 B1 2/2001 Jin JP 2003282788 10/2003 6,197,613 B1 3/2001 Kung JP 2006128662 5/2006 6,198,619 B1 3/2001 Fujioka JP 2006147810 6/2006 6,229,220 B1 5/2001 Saitoh TW 584950 4/2004 6,229,711 B1 5/2001 Yoneda W0 WO 87/01509 3/1987 6,238,599 B1 5/2001 Gelorme et al. ............ .. 252/514 6,250,541 B1 6/2001 Shangguan OTHER PUBLICATIONS Edelstein, D.C., “Advantages of Copper I-nterconnects,” Proceedings 6,323,426 B1 11/2001 Hoshizaki et 31‘ ““““ “ 174/70 R ofthe 12th Internat1onalIEEEVLSI Multrlevellnterconnectron Con6,332,988 B1 12/2001 Berger, Jr. ference (l995)pp. 301-307. 6,362,087 B1 3/2002 Wang Theng, C. et al. “An Automated Tool Deployment for ESD (Electro6,372,622 B1 4/ 2002 T2111 _ Static-Discharge) Correct-by-Construction Strategy in 90 nm Pro; gibayashl cess,” IEEE International Conference on Semiconductor Electronics

, , M18 (2004) pp. 61-67.

6,426,281 B1 7/2002 Lin Gao X et al “Anim - -

. , . . proved electrostatrc drscharge protectron structure for reducing triggering voltage andparasitic capacitance,” Solid6’452’270 Bl 9/2002 Hug; State Electronics, 27 (2003), pp. 1105-1110.

6,467,674 B 1 10/2002 Mihara Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and 634793900 B1 11/2002 Shinogi LoW-K Dielectrics in 65nm High Volume Manufacturing,” Elec6 495 397 B2 12/2002 Kubota tronrc om onents an ec no 0 on erence .

, , ‘c p dTh1gyCf 2006pp1611 6,501,169 B1 12/2002 Aoki 1615.

6,518,651 B2 2/2003 Hashimoto Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI 6,573,598 B2 6/2003 Ohllchi Circuits,”MaterialsResearch SocietySymposiumProceedingsVLSI 253313‘ 91 9/522:

7 ’ ung Roesch, W. et al. “Cycling copper flip chip interconnects,” Microg€g%gg‘ 3% $883 fifigjfma electronics Reliability, 44 (2004) pp. 1047-1054.

’ ’ Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and 6’653’5-63 B2 U/2003 Bohr Reliability,” International Electron Devices Meeting 2006 pp. 1-4. 6,661,100 B1 12/2003 Anderson . 6,683,380 B2 1/2004 Efland Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedrngs of

the 6th International Syrnpoisum on Physical & Failure Analysis of 6,707,159 B1 3/2004 Kumamoto I dC_ _ (1997) 121 124 6,709,985 B1 3/2004 Goruganthu ntegrate lrcults PP~ ' ~ 6,731,003 B2 5/2004 Joshi Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS 6,732,913 B2 5/2004 Alvarez ULSI Technology,” Technical Digest IEEE International Electron 6,762,122 B2 72004 Mall: Devices Meeting (1997) pp. 773-776. 6,809,020 B2 10 2004 S urai Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS 6,815,324 B2 11/ 2004 Huang Technology With Copper Metallization,” Technical Digest IEEE g/Ftta t International Electron Devices Meeting (1997) pp. 769-772. 6’864’l65 Bl 3/2005 Polyaéno 0 Jenei, S.et al.“HighQInductorAdd-on Module inThickCu/SiLKTM 6’940’169 B2 9/2005 Jingg single damascene,” Proceedings from the IEEE International Inter6:998:7l0 B2 2/2006 Kobayashi connect Technology Conference (2001) pp. 107-109. 7,008,867 B2 3/2006 Lei Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process 7,034,402 B1 4/2006 Seshan UtilizingaThick Metal Process Add-on Module,” Proceedings of the 7,098,127 B2 8/ 2006 Ito Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 1497,135,766 B1 11/2006 Costa 152.

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Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590. Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.

Bohr, M. “The NeW Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-66. Bohr, M. “The NeW Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) pp. 23-28.

Ingerly, D. et al. “LoW-K Interconnect Stack With Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing,” International Interconnect Technology Conference (2008) pp. 216-218.

Kurd, N. et al. “Next Generation Intel® Micro-architecture (Nehalem) Clocking Architecture,” Symposium on VLSI Circuits Digest of Technical Papers (2008) pp. 62-63.

Maloney, T. et al. “Novel Clamp Circuits for IC PoWer Supply Protection,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C, vol. 19, No. 3 (Jul. 1996) pp. 150-161. Geflken, R. M. “An Overview of Polyimide Use in Integrated Circuits and Packaging,” Proceedings of the Third International Symposium on Ultra Large Scale Integration Science and Technology (1991) pp. 667-677.

Lut11er, B. et al. “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices,” Proceedings of the 10th Inter

national IEEE VLSI Multilevel Interconnection Conference (1993) pp. 15-21.

Master, R. et al. “Ceramic Mini-Ball Grid Array Package for High Speed Device,” Proceedings from the 45th Electronic Components and Technology Conference (1995) pp. 46-50.

Maloney, T. et al. “Stacked PMOS Clamps for High Voltage PoWer Supply Protection,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings (1999) pp. 70-77.

Lin, M.S. et al. “A NeW System-on-a-Chip (SOC) Technologyi High Q Post Passivation Inductors,” Proceedings from the 53rd Electronic Components and Technology Conference (May 30, 2003) pp. 1503-1509.

MEGIC Corp. “MEGIC Way to system solutions through bumping and redistribution,” (Brochure) (Feb. 6, 2004) pp. 1-3.

Lin, M.S. “Post Passivation TechnologyTMiMEGIC® Way to System Solutions,” Presentation given at TSMC Technology Symposium, Japan (Oct. 1, 2003) pp. 1-32.

Lin, M.S. et al. “A NeW IC Interconnection Scheme and Design Architecture for High Performance ICs at Very LoW Fabrication CostiPost Passivation Interconnection,” Proceedings of the IEEE Custom Integrated Circuits Conference (Sep. 24, 2003) pp. 533-536. Wright, P; “Integrated Front-End Modules for Cell Phones”; 2005 IEEE Ultrasonics Symposium; pp. 564-572.

* cited by examiner

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