Timing comparator circuit for use in device testing apparatus

[54] TIMING COMPARATOR CIRCUIT FOR USE IN DEVICE TESTING APPARATUS

[75] Inventor: Hirokatsu Niijima, Gyoda. Japan

[73] Assignee: Advantest Corporation. Tokyo. Japan

[21] Appl. No.: 762,803

[22] Filed: Dec. 9, 1996

[30] Foreign Application Priority Data

Dec. 12, 1995 [JP] Japan 7-323321

[51] Int. CI.6 G04B 47/00; G04F 8/00;

G01R 31/28

[52] U.S. CI 368/10; 368/113; 324/73.1;

371/21.1; 371/25.1

[58] Field of Search 368/10. 113-120;

324/73.1, 158 R; 371/15.1. 21.1. 22.1-22.3,

25.1. 27

[56] References Cited

U.S. PATENT DOCUMENTS 4,070,565 1/1978 Borrelli 235/302

4,108,358 8/1978 Niemaszyk 235/302

4,994,732 2/1991 Jefirey et al 324/73.1

5212,443 5/1993 Westetal 324/158 R

5,311,486 5/1994 Alton et al 368/10

Primary Examiner—Vit W. Miska
Attorney, Agent, or Firm—Staas & Halsey

[57] ABSTRACT

A timing comparator circuit for use in device testing apparatus is provided which can eliminate, in the window comparison mode, an off time during which a failure cannot be detected. There are provided first and second window strobe pulse generating circuits S/RFF1 and S/RFF2 for alternately generating window strobe pulses, first and second failure detecting circuits 5a and 5b for detecting whether a failure signal exists or not in the output signals from a level comparator 2 during the pulse duration of each window strobe pulse supplied thereto from the first and the second window strobe pulse generating circuits, and first and second interleave circuits.

7 Claims, 6 Drawing Sheets