Ball grid array type semiconductor package having a flexible substrate

(54) BALL GRID ARRAY TYPE

SEMICONDUCTOR PACKAGE HAVING A
FLEXIBLE SUBSTRATE

(75) Inventors: Atsushi Fujisawa; Takafumi Konno;

Shingo Ohsaka, all of Hakodate; Ryo
Haruta; Masahiro Ichitani, both of
Kodaira, all of (JP)

(73) Assignee: Hitachi Hokkai Semiconductor, Ltd.,

Tokyo (JP)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 9 days.

(21) Appl. No.: 09/596,045

(22) Filed: Jun. 16, 2000

Related U.S. Application Data

(62) Division of application No. 09/126,438, filed on Jul. 30, 1998, now Pat. No. 6,232,650.

(30) Foreign Application Priority Data

Jul. 30, 1997 (JP) 9-204534

(51) Int. CI.7 H01L 23/495

(52) U.S. CI 257/666; 257/676

(58) Field of Search 257/666, 676;

438/126, 127, 123

(56) References Cited

U.S. PATENT DOCUMENTS

5,218,234 A 6/1993 Thompson et al 257/787

5,590,462 A 1/1997 Hundt et al 29/840

5,592,025 A 1/1997 Clark et al 257/774

5,756,380 A * 5/1998 Berg et al 438/126

5,874,784 A * 2/1999 Aoki et al 257/787

5,886,409 A 3/1999 Ishino et al 257/737

5,917,234 A * 6/1999 Tsuruzono 257/667

6,232,650 Bl * 5/2001 Fujisawa et al 257/666

FOREIGN PATENT DOCUMENTS

EP 0702404 9/1995

FR 0694965 1/1996

OTHER PUBLICATIONS

"Various Types of BGA Packages that Seal 100-MHz LSIs", Nikkei Electronics, Feb. 28, 1994, No. 602, pp. 111-117.

* cited by examiner

Primary Examiner—Phat X. Cao

(74) Attorney, Agent, or Firm—Antonelli, Terry, Stout & Kraus, LLP

(57) ABSTRACT

In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.

2 Claims, 22 Drawing Sheets