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(12) United States Patent
(io) Patent No.: (45) Date of Patent:
US 7,869,293 B2 Jan. 11,2011
(54) MEMORY SENSE SCAN CIRCUIT AND TEST INTERFACE
(75) Inventor: Stephen L. Morein, San Jose, CA (US)
(73) Assignee: Advanced Micro Devices, Inc.,
Sunnyvale, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 401 days.
(21) Appl.No.: 11/863,972
(22) Filed: Sep. 28, 2007
(65) Prior Publication Data
US 2009/0089632 Al Apr. 2, 2009
(51) Int. CI.
G11C 7/00 (2006.01)
(52) U.S. CI 365/205; 365/203
(58) Field of Classification Search 714/726;
327/202; 365/203,205 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,414,714 A * 5/1995 Gladden etal 714/731
5,485,466 A * 1/1996 Lyon et al 714/731
5,958,075 A * 9/1999 Wendell 714/726
6,111,794 A * 8/2000 Hoist 365/190
6,459,317 Bl* 10/2002 Lu et al 327/217
7,317,636 B2* 1/2008 Ideetal 365/185.22
7,514,975 B2* 4/2009 Frederick et al 327/202
7,560,965 B2* 7/2009 Waldrip et al 327/202
-James C Kerveros or Firm—Courtney IP Law
* cited by examiner
Primary Examiner (74) Attorney,
A scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command includes a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implement scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flipflop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.
10 Claims, 14 Drawing Sheets