United States Patent  [ii] Patent Number: 4,972,105
Burton et al.  Date of Patent: Nov. 20, 1990
4,881,202 11/1989 Tsujimoto et al 365/225.7 X
4,894,558 1/1990 Coiikle et al 364/716 X
4,910,418 3/1990 Graham et al 365/96 X
4,912,345 3/1990 Steele et al 307/468 X
4,912,348 3/1990 Maki et al 307/468 X
4,937,475 6/1990 Rhodes et al 364/716 X
Primary Examiner—Stanley D. Miller
Assistant Examiner—David R. Bertelson
Attorney, Agent, or Firm—Thomas O. Maser; John R.
A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.
9 Claims, 4 Drawing Sheets