requested via channel unit 22, execution unit 24, in- ternate data manipulator (ADM) unit 69 which also instruction unit 23, etc. eludes an associated comparator 70. The comparators
In general, the data processing system as set out in 68 and 70 compare bits 0 through 10 of the request ad
FIG. 1 is programmable and compatible with the IBM dress in the request address register 72 (index of main
system/370. 5 storage address —FIG. 1A) to the index of the lines
Referring now to FIG. 2 which shows the details of stored in primary storage 52 and alternate storage 53, console 27, as stated above, the system console would respectively. The results of these comparisons cause normally include a console computer 32 which is either the primary data manipulator 67 output or the termed a minicomputer. Such minicomputer has asso- alternate data manipulator 69 output to be loaded into ciatedwithita 1 2K memory 33 along with various con- 10 the proper output word register 65. This thus means trol interfaces. These include a disk controller 34 asso- that a line of data in main storage has a predictable lociated with a magnetic disk unit 36, a channel control- cation in either primary storage unit 52 or alternate ler 37 which is coupled to the channel of CH unit by a storage unit 53. In addition, as discussed in the aboveline 38, and a panel controller 39 which interfaces the mentioned Tobias application the data manipulators 67 system console with a control panel 41 which may in- 15 and 69 shjft data around in the proper sequence to ascludc, for example, toggle switches to allow the opera- sure proper alignment.
tor to physically modify the preprogrammed function xhe logic units 73> 74i 75 are the data request ports
of the console computer 32. An interface controller 42 (via the BAR) for the channe| unit (CHU), instruction
is coupled to a console control interface unit 43 which unit (IU) the executjon unit (EU). The EU makes its
interfaces from a data standpoint with the instruction 20 requests via the lv Data requests from and to the
unit, execution unit and storage unit on the lines as in- memory unit (MU) or high speed buffer (HSB) can be
dicated and also includes a scan out line 44 for pur- from any of the aboye ... pQrts
P0*" of transferring lhh ... or'nstructions- . „ PF logic unit 76 controls prefetch requests. The pre
FIG. 3 .llustrates the details of the storage unit 26 fetch algorithm is indicated in FIG. 4. The prefetch de
which mcludes a high speed buffer (HSB) 50 for stor- 25 ... js based on ^ fetch ^ ithrn and the
mg information and which can be accessed at the high ^ ^ ... ag ^ bg ... ^ be,ow
speeds of the c ock cycle time of the computer. Such Tu J . J r . L . *i
, „ . , . . , . , ,. v , The requesting data and prefetch ports, units 73
buffer includes indentical 256 line primary storage and ... . ,, . . .. •.
,„; B. , through 76, are all gated through the select unit 77
alternate storage units 52 and 53 alone with associated ,. ,, .. . . . . . . . ., „ . _ .
. . .. ,? re ■ J *a which has its output coupled back to the BAR 56 via
index units 54 and 55. High speed buffer 50 is ad- JU .. .. . r . . . , . _„
j J u .u Jj • »L if « Jj • . trle 'lne mcrementer 78 and byte adder 79.
dressed by the address in the buffer address register _, 3 .
,a A D > C£ u- u ■ i J J v . u c«! c .u The line mcrementer, upon a prefetch request, se
(BAR) 56 which is loaded by an input buss 57 from the .... ... c J. > TM . .
re .. , . . . IT-\n\ i.u . ■. lects the next line of data (32 bytes). The byte adder
effective address register (EAR) of the instruction unit , . ,
23 of FIG. 1. BAR 56 can also be loaded from channel f lectf uand keeP^ track of, the ^u^er lme^'"8 se'
unit 22. The information locations accessed in high 35 lected; however, data transfer to and from MS is always
speed buffer 50 result in the fetching or storing of the °n a f"' 1,ne basls' U thus re<>ulres four Passes to trans
corresponding information from or to main storage er a ine"
(MS), the execution unit, the channel unit or the in- Bnefly> ,n operation, the high-speed buffer 50 is ad
struction unit dressed by the buffer address register (BAR) 56. From
Communication to MS is via the 8 byte busses 58 and 40 the buffer address re8ister S6< a Portion of *he addre«
59. Such communication is discussed in greater detail <the index> is simultaneously gated to the primary buf
in the above copending Tobias application. The 8 bytes fer mdex 54 and alternate buffer index 55. The index
of data on buss 58 from main storage 21 are coupled unlts 54' 55 store bits 0 through 10 of the buffer ad
to the high speed buffer 50 by a Data In Register 60. dress register as illustrated in FIG. 1A. This address is
For data storage, the data in the Data In Register 60 is 45 associated with two unique storage locations—one
directed to either the primary or alternate portions 52, storage in the primary storage 52 and the other in the
53 of HSB 50. In addition to data from main storage on alternate storage 53. The low-order bits from the BAR
buss 58 the high speed buffer 50 also receives data 56, bits 11 through 18, are gated directly to the storage
from both the channel unit and execution unit indi- units 52 and 53.
cated by the four byte input busses 61 and 62. These 50 lf't >s a data request from the CHU or 1U and the reare processed by a store select and align unit 63 whose quired line of information is in the primary or alternate function again is more fully disclosed in the above- storage units, the data is then read out from the proper mentioned Tobias patent application. Data transfer location through the output word registers 65. If the from primary storage 52 and alternate storage 53 to MS data is not in the primary or alternate storage units 52, occurs on the associated busses 63 and 64 to the data 53, it must first be fetched from MS to the HSB where out register 66 which is coupled via buss 59 to main it is then processed through the output word register65 storage. This is on an eight byte basis. to the requesting unit. The data prefetch and replace On the other hand, for data requests, communication algorithms, infra, describe the transfer of data from MS between the high speed buffer 50 to the CPU and the 6Q to the HSB. Registers 73 through 76 are used in conchannel unit is on a 4 byte basis via the output word junction with such fetching. In the case of a prefetch of registers 65. The output word registers include an in- the next sequential line, the line incrementer 78 will struction word register, channel word register and op- provide the proper address for the prefetching of this erand word register. Data requests can come from the line. This is essentially controlled by the prefetch conCHU, IU or the execution unit (EU) via the IU. Regis- 65 trol unit 76. In other words, prefetch is accomplished ters 55 are connected to primary and alternate storage by the line incrementer 78, incrementing the existing 52, 53 by a primary data manipulator (PDM) unit 67 address in BAR 56 to form the full address of the next which includes an associated comparator 68 and an al- sequential line in the BAR.