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HIGH DENSITY PLD STRUCTURE WITH
FLEXIBLE LOGIC BUILT-IN BLOCKS
BACKGROUND OF THE INVENTION
This invention relates to a programmable logic device 5 (PLD) integrated circuit, and more particularly, the invention relates to a high density PLD with great flexibility and high performance using less memory than current PLDs.
The conventional way of constructing a PLD is to employ an AND gate array connected to an OR gate array, with 10 inputs to the AND array. Both AND OR arrays are programmable, in order to provide a desired logical output from the OR array.
The outputs from OR gates can be connected to a functionally configurable macrocell, whereby the OR outputs 15 can be latched, fed back to the AND array, or connected to I/O pins. The OR outputs can also be utilized as inputs to the AND array. The flexibility and capability of the macro cell can be increased by introducing into the cell configurable output-enables, configurable multiple selectors, config- 20 urable register clocks, register set and register reset signals.
The recent rapid development of semiconductor technology has made possible the design and manufacture of very complex integrated circuits. As a result, high density PLDs with very high flexibility and performance are commercially 25 available. In these PLDs, in order to maintain high capability, it is more effective to divide AND OR arrays into small logic blocks, and connect them with a global connection facility. Because of the relatively small size of arrays, earlier high density PLDs had only one register permanently 30 connected to every I/O pin. As the scale of arrays increased, the number of I/O pins was limited by package size and could not be increased accordingly. The logic capacity of PLDs was thus limited. Consequently, it is desirable to increase the number of registers with the concomitant 35 increase of array scale, i.e., to increase the registers per I/O pin. This requires circuits that are used to manage the outputs and feedback of increased registers.
The performance of the high density device depends heavily on how the logic blocks are constructed and how 40 they are connected together. Most of today's high density PLD products are constructed of logic blocks and a global interconnection, with all the logic blocks being connected together by the global interconnection, thus allowing information to be communicated between logic blocks. All the 45 outputs from the logic block are fed into the global interconnection and all the inputs to the logic block come from the global interconnection. With more than one register per I/O pin, these PLDs use I/O control block to handle the outputs, where outputs are multipexed. This structure offers 50 very high logic capability and is able to perform complex logic functions. However, three problems emerge with the structure. First with the number of registers per I/O pin increasing, a very complex I/O control block will result in more chip array area being used and low output perfor- 55 mance. The global interconnection becomes the bottleneck of device performance with all the feedbacks from the logic blocks inputting into it and all the inputs of logic blocks outputting from it, without any local feedback within logic blocks. Lastly, the controls of the macro cell are fed into the 60 cells in the same way as other logic signals, which also negatively affects the performance of the control signals.
SUMMARY OF THE INVENTION
An object of the invention is a high density PLD having 65 high performance and high flexibility while using less memory array.
Another object of the invention is a facility to effectively manage the outputs and feedbacks within a logic built-in block (LBB).
Yet another object of the invention is a dedicated control structure serving as both global and local control within a logic built-in block (LBB).
Briefly, an internal-oriented logic built-in block is constructed to build a high density PLD with high capacity and less chip area. The logic built-in blocks are connected via a global programmable interconnection array. To minimize the global connections, the logic built-in block is designed so that only some of the outputs from the multi-register macro cell are fed back to the PIA. However, to enhance the performance of the LBB, all the local outputs are locally fed back to a local AND array. Outputs of a multiple-register macro cell in the LBB are simply selected through a multiplexer, while allowing other non-selected registers to be buried registers, which function independently with selected outputs. This greatly increases the logic capability of the multi-register macro cell. To facilitate the control of multi-register macro cells, a special control AND array is used to generate the local and global control signals of macro cells within an LBB.
A feature of the invention is a high density PLD based on the LBB which comprises of AND-OR arrays and multiregister macro cells. This LBB construction provides high performance and great flexibility.
Another feature of the invention is that all outputs within an LBB are fed back to a local AND array, which enhances the local logic implementation capability.
Yet another feature of the invention is that the feedbacks to the PIA are configurable, which minimizes the load on the global interconnection.
Still another feature of the invention is that a dedicated control AND array is designed within an LBB to provide more flexible macro cell control.
The invention and objects and feature thereof will be more readily apparent from the following description and appended claims when taken with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a high density programmable logic device in accordance with one embodiment of the invention.
FIG. 2 is a block diagram of a logic built-in block (LBB) shown in FIG. 1, which includes two Configurable Logic Cells (CLCs) sharing a Control AND array.
FIG. 3 is a block diagram of a Configurable Logic Cell (CLC) as an independent construction element, with emphasis on accurate signal allocation, in accordance with an embodiment of the invention.
FIG. 4 is a block diagram of a Multi-Register Macro Cell (MRMC) shown in FIG. 3 and includes a logic control cell, I/O cell and all input-output connects.
FIG. 5 is a detailed schematic block diagram showing Logic Control Cell (LCC) construction which is a major part of the MRMC in FIG. 4.
FIG. 6 is a schematic block diagram, illustrating Input/ Output (I/O) cell construction which is a part of the MRMC in FIG. 4.
DESCRIPTION OF THE PREFERRED
A preferred embodiment of the invention is a high density programmable logic device (PLD) CMOS programmable
electrically-erasable logic device, which can be programmed by a logic designer to perform various kinds of logic functions. It includes interspersed pockets of function and interconnect. A user's logic function is programmed into the device, which is preferably based on electrically erasable 5 programmable read only memory (EEPROM) cells. Other kinds of programmable cells, such as static random access memory (SRAM) cells or programmable fuse/anti-fuse cells, may also be used as well. FIG. 1 is a block diagram of a PLD which shows its architecture in accordance with this embodiment of the invention. The device is constructed by connecting Logic Built-in Blocks (LBBs) 10 with a global Programmable Interconnection Array (PIA) 20. The device also employs a global clock buffer 30 to accept external clock inputs 16 and to generate a group of buffered global clocks 15 for synchronization purposes.
The logic built-in block 10 is a basic, but flexible functional element of this device. The LBB contains a large number of internal connections in order to perform logic functions relatively independently, while fewer signals are 20 sent to the programmable interconnection array 20 for the exchange of information with other logic built-in blocks. Logic built-in blocks receive external input from external I/O pins 14 and PIA input 13 from the programmable interconnection array which conveys information from other 25 LBBs. At the same time, to ensure that all the I/Os can feed inputs to every block of the device, logic built-in blocks feed all the Input/Feedback (IF) 12 into the global programmable interconnection array. To minimize the load on the interconnection array, instead of feeding all the outputs of an LBB 30 into the PIA, only some of them are sent to the programmable interconnection array as Global Feedback (GF) 11.
There are two levels of interconnection in the device: local interconnection, which is inside the logic build-in block, and global interconnection, which is provided by the 35 programmable interconnection array. The programmable interconnection array is a large array of switch matrices and is large enough to accommodate all of the LBB's global connections. It serves as a bridge to communicate logic information between LBBs, and enables multiple logic 40 built-in blocks to work together to implement a more complex logic function. Through global feedback 11, the logic signal generated by one logic built-in block may be sent to the interconnection array, then switched to other logic built-in blocks through the PIA input 13, to perform more 45 complex logic functions. The PIA also accommodates I/O pin inputs. The input/feedback 12 to the PIA utilizes the PIA as an input signal distributor to transfer external input signals to the LBB as appropriate.
The device provides four external dedicated clock pins 16 50 connected to the global clock buffer 30. The buffered clocks are connected to all the multi-register macro cells, in which the clock distribution circuit combines them with other LBB-wide or local clocks, and offers a versatile clocking scheme for the registers. By this mechanism, synchronous 55 clocking, asynchronous clocking and multi-clocking can be easily achieved through configuration according to the application.
The PIA could be implemented in different ways. In the present embodiment an AND array is used to perform the 60 interconnection. In addition to the interconnection, the array also provides an AND logic function. This kind of global interconnection increases the time taken to transfer signals, because all the gates of one column or row of EEPROM cells in the AND array are connected together, which results 65 in a large capacitive load. The speed of an implemented system depends strongly on how often the signals connect
ing the logic blocks in the LBB cross the PIA. The logic functions within LBB are quite fast, however when a function involves global connection, increasing global interconnections reduce speed of the system. One of purposes of this invention is to enhance the local feedback to provide faster logic function.
One major object, and a feature of the invention is a high capacity and more flexible logic block which can be used easily to construct a high density PLD in different scales and different capacities. In FIG. 1, a high density PLD with four LBBs is depicted. This is only a exemplar of the invention. Those who are skilled in art may easily double or triple the number of LBBs to achieve more complex logic function. In such a situation, more interconnections in the PIA are needed to convey signals between added LBBs.
FIG. 2 is a functional block diagram of the LBB in FIG. 1, which shows its major components and how they are assembled to form a desired logic function block. This LBB structure embodies features of the invention.
The LBB is generally constructed using two Configurable Logic Cells (CLCs) 40 sharing a dedicated control AND array 50. Each configurable logic cell contains a logic programmable AND-OR array (60, 70) followed by two groups of Multi-Register Macro Cells (MRMCs) 80 with each group having four multi-register macro cells.
The logic programmable AND-OR array is logically an AND gate array connected to an OR gate array, with inputs to the AND array being programmable to provide a desired logic output from the OR array. For logical convenience, a programmable AN-OR array is implemented by connecting one NAND array to another NAND array or connecting one NOR array to another NOR array. In this kind of array, the propagation delay is fixed, and independent of logic inputs. The fixed delay is determined by the total parasitic capacitance of the gates in a column or row. Therefore, the scale of the array and the design of the sense amplifier, which reads the logic value stored in the cells, will affect greatly the speed of the device. A typical example can be found in U.S. Pat. No. 4,124,899.
The Multi-register macro cell 80 is another novel structure of this invention. The cell contains a variable number of registers according to the logic capability requirement of the device. Its detailed structural explanation is given below.
From an overall point, the LBB consists of two AND-OR arrays (60, 70) connecting four groups of multi-register macro cells 80 sharing a dedicated control AND array, which serves as a universal control resource for the multi-register macro cells. Though the AND-OR arrays (60, 70) are physically separated in the LBB, they are logically connected as a whole, i.e., they have same inputs. The four groups of multi-register macro cells 80 have equal functionality, except that the local control signals from the control AND array 50 are different in each group.
The plenitude of connections in the LBB demonstrates the features of the invention. Every multi-register macro cell 80 has an external I/O pin 14. The I/O pins can be utilized as inputs to the AND array. The OR array 70 in every AND-OR (60,70) array is physically separated into two sub-OR arrays 70 and then every group of multi-register macro cell has its own corresponding OR array. A total of twenty four sum terms from the OR array in each configurable logic cell 70 is sent into the multi-register macro cell 80. There is a total of eight multi-register macro cells for each configurable logic cell, so each multi-register macro cell has three sum terms, one for every register. The multi-register macro cells use a device wide global clock signal 15 from the global