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TESTING SYSTEM FOR EVALUATING
INTEGRATED CIRCUITS, A BURN-IN
TESTING SYSTEM, AND A METHOD FOR
TESTING AN INTEGRATED CIRCUIT
TECHNICAL FIELD
This invention relates to systems for testing circuitry. More particularly, the invention relates to burn-in testing. The invention also relates to methods for conducting such tests.
BACKGROUND OF THE INVENTION
Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as "die" or "chips." Some circuits are formed on boards, such as printed circuit boards, such as where the cost of designing and manufacturing an integrated circuit chip is too high relative to the size benefit. These chips or boards define various circuits for use in computers (e.g., video cards, sound cards, modem cards, etc.), televisions, telephone systems, and many other electronic devices. The chips or cards also define the finished circuitry components of, for example, processors and memory circuits. Common types of memory circuits are DRAM and SRAM chips.
After a semiconductor wafer has been fabricated, not all chips provided on the wafer prove operable, typically resulting in less than 100% yield. Accordingly, individual dies must be tested for functionality. The typical test procedure for DRAM or SRAM circuitry is to first access the device via bonding pads on the individual die. Thereafter, the wafer is subjected to test probing whereby the individual die are tested for satisfactory operation. Inoperable die are typically marked by an ink mark. After testing, the wafer is cut into individual die. The operable, non-marked die are collected.
The operable individual die are then assembled in final packages of either ceramic or plastic to define a packaged integrated circuit or device. After packaging, the integrated circuits are loaded into burn-in boards which comprise printed circuit boards having individual sockets. The burn-in boards are placed into a burn-in oven, and the parts are subjected to burn-in testing during which the die are operated for a period of time at different temperature cycles, including higher than operating temperatures. The die are stressed to accelerate their lives in an effort to identify the weak die which are likely to degrade and fail under these tests. Manufacturers predict early failures, known as "infant mortalities", to occur within a predetermined period of time of the burn-in cycle. Burn-in testing is typically conducted for a period of time sufficient to reveal these infant mortalities. For example, if infant mortalities are expected to occur within twenty-four or forty-eight hours of burn-in testing, the burn-in tests can be completed within such time periods. In this manner, semiconductor wafer manufacturers can effectively test the quality of their integrated circuits in a reasonable time frame prior to shipping the integrated circuits to consumers.
More particularly, the failure rate for a semiconductor device as a function of time generally follows what is known as a "bathtub-type curve". The initial or infant mortality failure rate for die is very high at the start, and flattens out to near zero during a mid-time period, such as from one month through a period of 10 to 12 years, and then goes back up. In other words, if the integrated circuit survives the first one to five months or so of operation, it is highly probable that it will provide flawless operation through the tenth or
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twelfth year. Thereafter, usually after the expected lifetime of the device, material or other changes in the die cause the failure rate to increase exponentially, thus providing the bathtub shaped curve.
5 Burn-in testing can be conducted in either what is known as the static method or by a dynamic method. In both, the packaged die is electrically stressed under elevated temperature (e.g., 125° C.) for a given period of time (e.g., 24 hours) sufficient to test the die. Under a static electrical test, the die
1° is subjected to an operating voltage that is much higher than the normal operating voltage. For example, the Vcc node of the die may be subjected to an operating voltage of seven volts instead of the normal Vcc voltage of three to five volts, while the V„ node of the die is held at ground. Operability
15 is determined at the end of the test.
Under dynamic testing, individual devices are exercised on and off throughout the burn-in period, and the die is constantly monitored. Operability is determined during the test.
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On a burn-in board, several receptacles are provided on a burn-in board (e.g., two feet by three feet in size), and the individual packages are received. Wiring extends from these individual receptacles/devices to one edge of the board where they connect outwardly to the testing and intelligence cycling circuitry. These long lengths of line create undesired parasitics such as unwanted noise, capacitance, resistance, inductance and crosstalk.
As described above, the die are subjected to a preliminary
3Q wafer-level test before sawing into individual die, and a burn-in test after separating and packaging of the individual die. Each of these two separate tests require some physical connection with a testing apparatus. During the wafer-level test probes are employed to directly contact bonding pads.
35 During the burn-in testing, each individual chip is inserted into a socket on a burn-in board for the test.
Attention is directed to commonly assigned U.S. patent application Ser. No. 07/979,607, filed Nov. 20, 1992, titled "Testing and Burn-In of IC chips Using Radio Frequency
4q Transmission," which is incorporated herein by reference.
SUMMARY OF THE INVENTION
The invention provides a system and method for preliminary wafer-level testing and burn-in testing without physi
45 cally contacting the semiconductor wafer or individual die. In accordance with one aspect of the invention, a contactless method of burn-in testing semiconductor devices is provided wherein a burn-in board is equipped with an RF transmitter/receiver. Another transmitter/receiver is pro
50 vided remote of a bum-in furnace such that test logic can be sent via radio frequency to each individual burn-in board during burn-in tests. The burn-in board has separate power lines for the Vcc and V„ node connections to the respective semiconductor devices.
55 One aspect of the invention provides a burn-in testing method and system for evaluating a circuit under test. A burn-in board has a plurality of receptacles. At least one of the receptacles is sized to receive the circuit under test. Test interface circuitry is supported by the board and coupled to
60 the receptacles. The test interface circuitry includes a transmitter and receiver. Power conductors are supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing. A burn-in oven has a compartment
65 selectively receiving the burn-in board and being configured to apply heat within the compartment. An interrogator unit has a radio communication range extending to the test
interface circuitry. The interrogator unit is configured to send commands to the test interface circuitry to exercise the circuit under test via radio communication and to receive responses to the commands via radio communication.
In one aspect of the invention, the test interface circuitry 5 is mounted to the board. The power conductors comprise conductive traces formed on the board. Conductive traces formed on the board couple the receptacles to the test interface circuitry.
In one aspect of the invention, the interrogator unit is 10 configured to provide an identification code as part of the interrogating information. The test interface circuitry includes ID labels assigned to respective receptacles, and the test interface circuitry is configured to compare the identification code provided by the interrogator unit with the ID 15 label of the receptacle for the circuit under test, the test interface circuitry being configured to test cycle the operational circuitry when the identification code matches the ID label. The test interface circuitry is separately coupled to the respective receptacles such that the interrogator, in commu- 20 nication with the test interface circuitry, can select a receptacle, and thereby select a desired one of a plurality of circuits under test, for test cycling.
In one aspect of the invention, the receptacles respectively comprise sockets sized to receive an integrated circuit.
In one aspect of the invention, the testing system is configured to perform dynamic testing. In dynamic testing, the circuitry being tested is cycled on and off during a period of time. For example, the period of time may be greater than 3Q twelve hours. More particularly, the period of time may be both greater than twelve hours and less than 36 hours. In one aspect, during the dynamic testing, the oven heats the chamber to a temperature greater than 100 degrees Celsius.
In one aspect of the invention, the testing system is 35 configured to perform static testing.
In one aspect of the invention, the power conductors extend at least partially along the board. In one aspect, the burn-in oven includes a power source accessible from the chamber, and the power conductors are removably coupled 40 to the power source. The power source is configured to supply to the circuit under test a voltage higher than the normal operating voltage of the circuit under test.
In an alternative embodiment, the test logic is sent to the burn-in board by light. More particularly, a testing system 45 comprises a burn-in oven defining a chamber, and an interrogator unit having an optical transmitter directed into the chamber. The optical transmitter has an optical communication range. The interrogator unit is configured to optically transmit interrogating information into the chamber. A burn- 50 in board is selectively received within the chamber, remotely from the interrogator unit, but within the optical communication range. The burn-in board includes a plurality of receptacles sized to receive respective circuits under test. The burn-in board has an optical receiver configured to 55 communicate with the transmitter.
One aspect of the invention provides a method for testing an integrated circuit having operational circuitry. A burn-in board is provided having a plurality of receptacles configured to receive integrated circuits and to electrically inter- 60 face with the operational circuitry in the integrated circuits. Test interface circuitry is formed on the burn-in board, electrically coupled to the receptacles. An interrogator unit is provided, and the burn-in board is located remotely from the interrogator unit. The integrated circuit is placed in one 65 of the receptacles. Power is supplied to the operational circuitry and the test interface circuitry. Interrogating infor
mation is coupled to from the interrogator unit to the test interface circuitry on the burn-in board via radio communication.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 is a perspective view of a testing system according to one aspect of the present invention.
FIG. 2 is a plan view of a testing system according to another aspect of this invention.
FIG. 3 is a block diagram of electrical components of the testing system of FIG. 1.
FIG. 4 is a block diagram of electrical components of the testing system of FIG. 2.
FIG. 5 is a block diagram of electrical components of the testing system of FIG. 2 in accordance with an alternative embodiment of the invention.
FIG. 6 is a block diagram illustrating of electrical components of the testing system of FIG. 2 in accordance with another alternative embodiment of the invention.
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).
FIG. 1 diagrammaticaily illustrates a testing system 10 according to one embodiment of this invention. The testing system of this invention can be used to test multiple devices or circuits under test 12, such as circuit cards or integrated circuits (ICs), at the same time. In the illustrated embodiment, the term "integrated circuit" is defined as including a package, a chip in the package having circuitry, and pins extending from the package and being connected to the circuitry. The devices under test 12 include operational circuitry which comprises the components and elements for performing functions which the integrated circuit is designed to perform. For example, if the integrated circuit is a RAM or ROM integrated circuit, the operational circuitry comprises the memory cells, the circuitry for selecting a particular cell for reading or writing, and other circuitry typically found in a RAM or ROM.
In the embodiment shown in FIG. 1, the testing system 10 employs radio communication with a transponder on a burn-in board to interrogate individual integrated circuits without physically contacting them.
The testing system 10 includes one or more substantially identical burn-in boards 14. For purposes of simplicity, only one such board will be described. The board 14 shown in FIG. 1 has a plurality of receptacles 16. The receptacles 16 are sized to receive the devices under test 12. In one embodiment, the board 14 has a plurality of rows and columns of receptacles sized to receive integrated circuits.
The testing system 10 further includes test interface circuitry 18 electrically coupled to the receptacles 16. In the embodiment of FIGS. 1 and 3, the test interface circuitry is supported by (e.g., mounted to) the respective boards 14. In one alternative embodiment, the test interface circuitry is included in the devices under test 12. The system includes conductive traces 19 formed on the board electrically coupling the receptacles 16 to the test interface circuitry 18. The
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