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SINGLE LOAD, MULTIPLE ISSUE QUEUE WITH ERROR RECOVERY CAPABILITY
FIELD OF THE INVENTION 5
The present invention relates to an apparatus and a method for issuing high performance transfers of information from a central processing unit (CPU) within a computer to another location within that computer, while still enabling the CPU to recover from transmis- 10 sion errors on a per transaction basis.
BACKGROUND OF THE INVENTION
Computer systems are typically made up of multiple nodes which are connected together by a system bus 15 which carries information, such as commands, addresses, data, and control signals between the nodes. Examples of the nodes which make up common computer configurations include central processing units, main memory, and I/O adapters/controllers, which 20 provide interfaces to mass storage devices and networks. When information is transferred over a bus the receiving node will inform the transmitting node whether that information was corrupted during transmission and whether there were any other protocol 25 errors resulting from the transaction. In part, this is accomplished by checking parity bits, which are transferred along with the information.
When the receiving node has confirmed that the transmission is error-free, it will send back an acknowl- 30 edgment ("ACK") signal to the transmitting node indicating that the information is good. Alternatively, if the information has been corrupted in transmission or any other bus protocol error occurs, the transmitting node does not return an ACK. This failure to return an ACK 35 during the time period required by the bus protocol is logically understood by the transmitting node as a 'noacknowledgment' ("NACK") signal indicating that the information is not good, and the transmitting node must once again transmit that information. 40
There is some time delay between the completed transmission of the information to the receiving node, and the determination by the receiving node whether the information was corrupted during transmission and whether there were any other protocol errors. This is 45 because there must be some time for the information to be checked against the parity bit by the bus interface of the receiving node. Thus, if the transmitting node sends information during a first bus cycle, it is common for that node to wait some number of bus cycles before it 50 has an ACK or NACK informing it whether that information is good.
System designs known in the computer architecture art often employ the use of queues for the temporary storage of information which is bound for transmission 55 from one node to another. In a typical implementation, a queue is positioned between a CPU and the interface to the system bus. The CPU will load the queue with information that is to be transferred from the CPU to main memory. An advantage of using the queue in this 60 fashion is that it enhances CPU performance by allowing the CPU to continue processing additional operations before the actual completion of the transfer to main memory. In addition, in the typical implementation the loading of the queue takes place at the same rate 65 at which the CPU operates, which is necessary for maximum performance. The amount of information stored by a output queue is usually sufficient to com
prise several transactions. Therefore, a CPU which has a queue is capable of issuing multiple, immediately successive transactions on the system bus as the queue is unloaded.
Although an output queue can issue such multiple, immediately successive transactions, the conventional approach to unloading a queue does not take advantage of this capability because of the need of the system to recover from transmission and bus protocol errors. Specifically, when a NACK results from a given transaction, the system must be able to reissue the transaction so that the information is once again sent from the transmitting node to the receiving node. This conventional approach requires that no successive transaction be commenced until there has been a successful completion of the preceding transaction, or until continuous unsuccessful attempts at transmission of the same information result in a terminating error, known as a "time out".
If, for example, the transmitting node were to commence a second transaction before receiving all of the error information relating to the first transaction, and the first transaction results in an error, the control subsystem of the transmitting node will have to jump back and retransmit the first transaction after transmitting the second transaction. Then, assuming the second transaction is error-free, after the repeated execution of the first transaction, the control sub-system would have to jump ahead to the third transaction, given that there is no need to repeat the second transaction, which was successful. Such a jump back - jump ahead scheme has proven extremely complex, and therefore has not been implemented.
Accordingly, under the conventional unload method, when the information contained in the first queue entry address is transmitted, the system will wait until all of the ACK's have been returned before transmitting the information contained in the second queue entry address. If, however, a NACK is returned, the transaction is repeated. The disadvantage of this approach, however, is that system performance is degraded because the further unloading of the queue is stalled while the node is forced to wait for the ACK's or NACK's relating to a given transaction to be returned. This disadvantage is rather significant in light of the continuing trend for the speed of CPU's to increase, which thereby places a greater demand on system interconnects to issue transactions in an immediately successive order. On the other hand, if the output queue's ability to issue multiple, immediately successive transactions is to be used, the design of the unload system for the queue must be capable of recovering from errors when the original or subsequently attempted transactions result in at least one NACK. Such error recovery capability is a protocol requirement of some advanced system buses.
In accordance with an aspect of the present invention, there is provided a single output queue which is loaded through one set of load circuitry which operates at the same speed as the CPU.
In another aspect of the invention the single output queue is logically divided into two separate logical queues; the two logical queues being made up of those physical queue entry address locations that are even, and those physical queue entry address locations that are odd.
Another aspect of the invention is to access the odd and even queue entry addresses through two separate
sets of unload circuitry, which thereby permits rapid unloading of the queue and enhances system performance.
Still another aspect of the invention is to alternate between the unloading of odd and even queue entry 5 addresses so that while one transaction is underway, the immediately preceding transaction can check its own error information to determine whether it should resend the information in the same queue entry address again, or proceed to the next queue entry address. Moreover, 10 this determination by the first half of the logical queue is done independent of the transaction issuance state of the other half of the logical queue. Therefore, the dual access system permits unloading at high performance, but also provides a sophisticated method of error recov- 15 ery which is practical to implement.
SUMMARY OF THE INVENTION
In accordance with the present invention, an output queue for writing information from a CPU to main 20 memory is logically divided into its odd and even queue entry addresses. The queue has a single load path on its input side, allowing the loading speed to be the same as the operating speed of the CPU. Associated with the queue is a dual set of unload circuitry, one set of which 25 accesses the odd queue entry addresses and the other accesses the even queue entry addresses. Further associated with each set of unload circuitry is an address pointer and error response circuitry. Ultimately, the unload circuitry is connected to the system bus for 30 transmitting information out of the queue to main memory.
After the queue is loaded with information it is emptied through the unload circuitry. Specifically, the even address circuitry accesses the information stored in the 35 first even queue entry address, and transmits that information to main memory. Immediately thereafter, the odd address circuitry accesses the information stored in the first odd queue entry address and transmits that information to main memory. While the second transac- 40 tion is underway, parity and protocol error information relating to the first transaction is evaluated by the error response circuitry to determine whether the address pointer for the even queue entry addresses should be advanced to the next even address of the queue. If an 45 error in the first transaction is detected, the address pointer will be stalled so that immediately following the completion of the second transaction, the first transaction will be repeated.
Likewise, while the information in the first even 50 queue entry address is being retransmitted, parity and protocol error information relating to the second transaction is evaluated by the error response circuitry to determine whether the address pointer for the odd queue entry addresses should be advanced to the next 55 odd queue entry address. Assuming that the second transaction was error-free, the odd address counter will advance so that the second odd queue entry address information will be transmitted as soon as the retransmission of the first even queue entry address is com- 60 pleted.
The unloading of the queue will generally continue this ordered sequence of accessing odd and even queue entry addresses in like fashion until the queue is empty. Thus, the queue functions as a high performance inter- 65 face between the CPU and main memory, being loaded on its input side at the same operating speed as the CPU. Moreover, due to its ability to reissue a transaction
which resulted in an error, the queue can continue high performance operation even under error recovery conditions.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a general system overview showing multiple CPU modules each having a write-back queue, multiple 1/0 modules, and multiple main memory modules all linked together by a system bus.
FIG. 2 is an illustration of the output queue with its related load and unload circuitry.
FIG. 3 is a more detailed illustration of the output queue, using a three dimensional characterization to show the multiple blocks of information stored in the individual queue entry address locations.
FIG. 4 is a representation of the D latches that comprise the output queue storage locations.
FIG. 5A is a timing diagram that shows the performance of an output queue using a conventional, single unload approach, while FIG. 5B is a similar timing diagram that shows the performance of an output queue using the dual unload approach of the present invention.
FIG. 6 illustrates an alternate embodiment of the present invention, showing multiple, dual unload output queues linked together to achieve even higher transaction performance than one, dual unload output queue.
DESCRIPTION OF THE PREFERRED
The present invention relates to a queue which is loaded through one set of load circuitry which operates at the high performance speed of the CPU, and unloaded through multiple sets of unload circuitry. The exact number of sets of unload circuitry is determined by logically dividing the queue into some number of interleaved, queue entry addresses and issuing transactions from those addresses in an ordered sequence. Consequently, through using this interleaved, transaction issuance approach the queue provides a high performance interface with the system bus.
In the preferred embodiment of the invention the queue is designed to write information from a CPU to main memory through the use of a single, circular queue with dual unload circuitry. A circular queue is a queue which is loaded with information, and as it is unloaded, the queue entry addresses which have been emptied are then available for additional information to be loaded again. The use of this queue substantially improves system performance by having transactions on the system bus proceed one right after the other, without any given transaction having to be acknowledged as errorfree before commencing the next transaction. The issuance of transactions in this manner, namely commencing one transaction before receiving back complete error information regarding the immediately preceding transaction, shall hereafter be defined as "multiple, immediately successive transactions". In addition, even though transactions can proceed in this tightly ordered sequence, the interleaved write-back approach is capable of recovering from transmission errors using a sophisticated, but practical to implement, error recovery scheme.
Referring now to the drawing, FIG. 1 shows a computer system, including multiple, identical CPU modules 20(a-n), multiple, identical input/output (I/O) modules 22(a-n), and multiple, identical main memory modules 24(a-n). The illustration shows 'n' number of CPU modules, I/O modules, and main memory modules be