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TRANSISTOR STRUCTURE AND METHOD
This is a Divisional application of Ser. No.: 09/895,697 filed Jun. 29, 2001, which is presently pending.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits, and more specifically, to the ultra largescale fabrication of submicron transistors.
2. Discussion of the Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VLSI) circuits, such as microprocessors, memories, and applications specific integrated circuits (ICs). Presently, the most advanced ICs are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.5 fim. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 fim. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply "scaled down" to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor 100 is shown in FIG. 1. Transistor 100 comprises a gate electrode 102, typically polysilicon, formed on a gate dielectric layer 104 which in turn is formed on a silicon substrate 106. Apair of source/drain extensions or tip regions 110 are formed in the top surface of substrate 106 in alignment with outside edges of gate electrode 102. Tip regions 110 are typically formed by well-known ion implantation techniques and extend beneath gate electrode 102. Formed adjacent to opposite sides of gate electrode 102 and over tip regions 110 are a pair of sidewall spacers 108. A pair of source/drain regions 120 are then formed, by ion implantation, in substrate 106 substantially in alignment with the outside edges of sidewall spacers 108.
As the gate length of transistor 100 is scaled down in order to fabricate a smaller transistor, the depth at which tip region 110 extends into substrate 106 must also be scaled down (i.e., decreased) in order to improve punchthrough characteristics of the fabricated transistor. Unfortunately, the length of tip region 110, however, must be larger than 0.07 fim to insure that the later, heavy dose, deep source/drain implant does not swamp and overwhelm tip region 110. Thus, in the fabrication of a small scale transistor with conventional methods, as shown in FIG. 1, the tip region 110 is both shallow and long. Because tip region 110 is both shallow and long, tip region 110 exhibits substantial parasitic resistance. Parasitic resistance adversely effects (reduces) the transistors drive current.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an illustration of a cross-sectional view of a conventional transistor.
FIG. 2 is an illustration of a cross-sectional view of a transistor in accordance with the present.
FIGS. 3A-3G illustrates a method of fabricating a transistor in accordance with the present invention.
DETAILED DESCRIPTION OF THE PRESENT
A novel transistor and its method of fabrication is described. In the following description numerous specific
details are set forth, such as specific materials, dimension and processes etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the invention may be
5 practiced without these specific details. In other instances, well-known semiconductor equipment and processes have not been described in particular detail in order to avoid unnecessarily obscuring the present invention.
The transistor of the present invention includes a silicon
10 on insulator substrate with an ultra thin body of less than 500 nanometers which is ideal for sub-threshold slope and device scalability. Additionally, the transistor channel is formed of intrinsic or undoped epitaxial silicon which provides a transistor with high mobility and minimal thresh
15 old voltage (Vt) fluctuation. The present invention includes a polysilicon/mid-gap metal composite gate electrode for pinning the threshold voltage and eliminating poly depletion. Additionally, the CMOS structure can include a raised tip and raised source/drain architecture for low external
20 parasitic resistance. The novel transistor structure of the present invention is ideal for low Vdd (less than 1.0 volts) and low power applications for 70 nanometer technology and beyond. The device has zero poly depletion, ideal sub-threshold slope, zero dopant fluctuation and very low
25 external resistance.
A novel transistor 200 in accordance with the present invention, is illustrated in FIG. 2. Transistor 200 is formed on an insulating substrate 202. In an embodiment of the present invention, the insulating substrate comprises an
30 oxide film 204, such as silicon dioxide, formed on a monocrystalline silicon subs-rate 206. In other embodiments the insulating substrate can be other insulating substrates such as, for example, diamond, sapphire, quartz, non conducting polymers, gallium arsinide, and wide band gap semiconduc
35 tors. Transistor 200 includes a very thin intrinsic or undoped epitaxial silicon body or channel 208 formed on insulating substrate 202. The thickness of the intrinsic or undoped silicon body is less than 500 A and preferably less than 100 A and ideally less than 30 A. In an embodiment of the
40 present invention, the thin silicon body is at most very slightly doped to a concentration of less than lxlO15 atmos/ cm3. Ideally, however, intrinsic silicon body is completely undoped and has no carriers other than the intrinsic carriers of approximately than lxlO14 atom/cm3. A gate dielectric
45 layer 210, such as but not limited to a silicon dioxide film or a silicon oxynitride film, is formed directly onto the top surface 203 of intrinsic silicon body 208. In an embodiment of the present invention, the gate dielectric 210 is a nitrided oxide film having a thickness less than 50 A and preferably
50 less than 15 A.
A gate electrode 212 is formed directly on gate dielectric layer 210. Gate electrode 212 is a composite electrode having a mid-gap work function film 214 formed directly on gate dielectric 210 and a heavily doped polysilicon film 216
55 formed on the mid-gap work function film 214 as shown in FIG. 2. Mid-gap work function film 214 has a work function dose to the mid-gap of silicon (i.e., between the work function of n+ ploy (approximately 4.2 eV) and p+ poly (approximately 5.2 eV)) and preferably has a work function
60 between 4.65 eV to 4.9 eV. Examples of suitable mid-gap work function films include but are not limited to titanium nitride (TiN), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), polycrystalline carbon, and metallic silicides, such as titanium silicide. In a preferred embodi
65 ment of the present invention, the mid-gap work function film is titanium nitride. In an embodiment of the present invention, the mid-gap work function film 214 has a thick3
ness less than 100 A and can have a thickness as thin as one monolayer or about 3-5 A. The polycrystalline silicon film 216 can have a thickness of approximately 1000 A.
A pair of thin sidewall spaces 218 having a width of 100 A or less is formed along opposite sides of gate electrode 5 212 as shown in FIG. 2. Spacers 218 electrically isolate gate electrode 212 from a doped silicon or silicon alloy film 220 used to form raised tip 232 and raised source/drain contact regions 236. Sidewall spacers can be formed from a dielectric film, such as but not limited to silicon dioxide and silicon 10 nitride. Transistor 200 can also include a second pair of sidewall spacers 222 formed adjacent to the outside edges of first sidewall spacers 218. The second pair of sidewall spacers 222 are wider than the first pair of sidewall spacers 218 and in an embodiment of the present invention have a ^ width of between 500-1500 A. The second pair of sidewall spacers 222 are used to define the raised tip region and the contact regions and can be used to prevent silicide encroachment when forming silicide on the contact regions in a salicide process. 20
Transistor 200 includes a pair of source/drain regions 230 formed along opposite sides of intrinsic silicon body or channel 208 as shown in FIG. 2. Each source/drain region 230 includes an ultra shallow tip or extension region 232, a raised tip or extension region 234, and a raised contact 25 region 236. The ultra shallow tip portion 232 is formed of doped epitaxial silicon 235 formed by out diffusion of dopants into the intrinsic silicon beneath the first pair of sidewall spacers and slightly beneath the outside edges of gate electrode 212 as shown in FIG. 2. The ultra shallow tip 30 regions 232 typically extend at least 100 A beneath (laterally) gate electrode 212 for a transistor with an effective gate length of less than 0.1 microns (or 1000 A). Additionally, ultra shallow tip region 232 has a thickness which extends from beneath gate dielectric 210 to insulating 35 substrate 202. Raised tip region 234 is located beneath second sidewall spacer 222 and is adjacent to the outside edges of first sidewall spacer 218. Raised tip region 234 is formed of a doped silicon or silicon alloy 220 selectively deposited onto the intrinsic silicon film used to form intrin- 40 sic body 208. Additionally, raised tip extension region 234 includes a portion 235 doped by "out diffusing" dopants from the selectively deposited silicon or silicon alloy into the underlying intrinsic silicon film. Because a portion of the raised tip region 234 is formed above semiconductor sub- 45 strate surface 203 on which the gate dielectric layer 210 is formed, raised tip region 234 is said to be "raised". A raised tip region significantly reduces the parasitic resistance of transistor 200 and thereby improves its performance.
Transistor 200 can also include a pair of source/drain 50 contact regions 236 form adjacent to the outside edge of second sidewall spacers 222. Source/drain contact regions 236 comprise selectively deposited silicon or silicon alloy 220 and "out diffusion" doped intrinsic silicon region 235. Source/drain contact regions are raised contact regions. 55 Silicide 240 can preferably be formed on source.' drain contact regions 236 in order to help reduce the contact resistance of transistor 200. Additionally, silicide 240 is also preferably formed on silicon or silicon alloy film 220 on gate electrode 212. Both raised contact region 236 and raised tip 60 or extension region 234 and shallow tip region extend down to insulating substrate 202.
The transistor 200 of the present invention has high mobility because the channel 208 is undoped or intrinsic silicon. Additionally, transistor 200 has a very steep sub- 65 threshold slope which gives the transistor good short channel effects which improves the devices scalability. The
transistor 200 of the present invention has a low threshold voltage (Vt) because the channel or body 208 of the transistor is undoped or intrinsic silicon. The use of a mid-gap work function film as the lower layer of the gate electrode has the effect of raising the threshold voltage of the device which is necessary because of the use of intrinsic or undoped silicon for the body. A low threshold voltage is desirable for low operating voltages (Vcc) or less than 1.0 volt and low power operations because the drive current (Irf) of transistor 200 is proportional to the operating voltage (Vcc) minus the threshold voltage (Vt). Additionally, because transistor 200 has a thin channel body 208, transistor 200 has a steep threshold slope which gives the transistor 200 a low off current (Ioff). Alow off current (Ioff) is necessary to operate a transistor with a low threshold voltage. In current MOS transistors, if Vt is too low the off current is unacceptably high.
Additionally, the transistor of the present invention does not suffer from threshold voltage fluctuations because of the use of intrinsic silicon or undoped silicon body. Since there are no dopants in the channel region 208 of the device, the dopant concentration from transistor to transistor across the wafer or substrate does not vary and each device has the same threshold voltage which is determined by the type of mid-gap work function metal 214 used in the gate electrode. Additionally, the use of raised tip and raised source/drain contact regions has the effect of making for low external parasitic resistance for the device. It is to be appreciated that if the tip region 234 and the source/drain contact regions 236 were not raises the device would suffer from high parasitic resistance due to the thinness (less than 500 A) of the epitaxial silicon film formed on the insulating substrate. Additionally, because a metal film is used as the lower layer in the gate electrode of the device, the device does not suffer from poly depletion effects. (Poly depletion effects are caused by not having enough dopants in the lower portion of a polysilicon film when polysilicon is used to form the gate electrode of a device).
As such, the features of the present invention such as a thin channel or body, an intrinsic epitaxial silicon channel, a mid-gap work function gate electrode, raised tip and source/drain contact regions, all work in combination with one another to produce a device which is characterized by high mobility, minimal Vt fluctuation, low external parasitic resistance, no poly depletion, steep sub-threshold slope, and good device scalability making the transistor 200 of the present invention ideal for use in low voltage and low power operations in 70 nanometer technology and beyond.
Illustrated in FIGS. 3A-3G is a method of fabricating the transistor of the present invention. The transistor of the present invention is fabricated on an insulating substrate 302 as shown in FIG. 3A. In an embodiment of the present invention, insulating substrate 302 includes a lower monocrystalline silicon substrate 304. Formed on the monocrystalline silicon substrate 304 is an insulating oxide 306 having a thickness greater than or equal to 1000 A. Alternatively, insulating substrate 302 can be other types of insulating substrates, such as but not limited to a graphite substrate, a diamond substrate, a sapphire substrate, a quartz substrate, or a gallium arsinide substrate. Formed on top of insulating substrate 302 is a thin intrinsic silicon epitaxial film 308. Intrinsic silicon epitaxial film 308 is formed thin and has a thickness less than 500 A and preferably less than 100 A and ideally less than 30 A. Intrinsic silicon epitaxial film 308 is preferably undoped silicon which has not been intentionally doped with impurities. If intrinsic epitaxial silicon film 308 is doped, it is only very slightly doped to a
concentration less than lxlO15 atoms/cm3. If intrinsic epitaxial silicon layer 308 is slightly doped, it would be doped with a conductivity type with is opposite the conductivity type of which the source/drain regions will be formed. A substrate as shown in FIG. 3A having a silicon epitaxial film 5 308 formed on an oxide 306 is known as a "silicon on insulator" (SOI) substrate. Intrinsic epitaxial silicon film 308 is used to form the thin body or channel of the transistor of the present invention.
Next, as shown in FIG. 3B, a gate dielectric layer 310 is 10 formed directly on intrinsic silicon body 308. In an embodiment of the present invention, gate dielectric layer 310 is a nitrided oxide layer formed to a thickness between 15-30 A. It is to be appreciated that other well-known gate dielectrics, such as oxides, nitrides, and combinations thereof may be 15 utilized, if desired. In an embodiment of the present invention, the gate dielectric is a thermal oxide which is grown by heating the substrate in an oxygen ambient. The thermal oxide is then nitrided utilizing a remote plasma nitridation process. Next, as also shown in FIG. 3B, a metal 20 film 212 halting a mid-gap work function is deposited directly onto dielectric layer 310. Mid-gap work function film 312 has a work function between n+ polysilicon (4.2 eV) and p+ polysilicon (5.2 eV). In an embodiment of the present invention, mid-gap work function film 312 has a 25 work function between 4.65 eV to 4.9 eV. In an embodiment of the present invention, the mid-gap work function film is titanium nitride and can be formed by well-known techniques such as sputtering or chemical vapor deposition (CVD). Other suitable mid-gap work function films include 30 but are not limited to tungsten, titanium, molybdenum., tantalum, and metallic silicides. Mid-gap work function metal 312 is preferably formed to a thickness of less than 100 A. Next, a polycrystalline silicon film 314 is blanket deposited over and directly onto mid-gap work function film 35 312 as shown in FIG. 3B. Polysilicon film 314 can be formed with well-known techniques to a thickness of approximately 1000 A. The polysilicon film 314 can be doped during the deposition (i.e., insitu doped) or can be doped by ion-implanting after the formation of film 314, or 40 can be subsequently doped during the source/drain doping of the transistor.
Next, polysilicon film 314, mid-gap work function film 312, and gate dielectric layer 310 are patterned with wellknown photolithography and etching techniques to form a 45 gate electrode 316 from polysilicon film 314 and mid-gap work function film 312.
It is to be appreciated that other well-known patterning techniques may be utilized to pattern polysilicon film 314 and mid-gap dielectric film 312 including submicronlithog- 50 raphy techniques, such as ebeam and x-ray, and sublithographic patterning techniques such as described in U.S. Pat. No. 5,434,093 entitled INVERTED SPACER TRANSISTOR and assigned to the present assignee. In an embodiment of the present invention, gate electrode 316 has a drawn 55 length ("L") of 100 nanometers or less and preferably 70 nanometers or less.
Next, as shown in FIG. 3D, a pair of thin dielectric sidewall spacers 318 are formed on intrinsic silicon film 308 and along opposite sidewalls of gate electrode 316. Sidewall 60 spacers 318 can be formed to a thickness between 50-150 A with 100 A being preferred. Sidewall spacer 318 can be formed with well-known techniques such as by blanket depositing a dielectric layer used to form the spacers over the entire substrate including intrinsic silicon layer 308 and 65 gate electrode 316 to a thickness desired for the width of the sidewall spacers 318, and then anisotropically etching the
dielectric film to remove the dielectric from horizontal surfaces and leaving sidewall spacers 318 adjacent to laterally opposite sidewalls of gate electrode 316. It is to be appreciated that spacers 318 must have a width sufficient to electrically isolate a subsequently deposited silicon or silicon alloy film from gate electrode 305. Additionally, the width of the silicon nitride spacers 318 defines the minimum length of the ultra shallow tip portion of the fabricated transistor.
In an embodiment of the present invention, sidewall spacers 318 are formed by a "hotwall" process to provide a very hermetic seal of gate electrode 316 and the edges of gate dielectric 310. Additionally, although hotwall silicon nitride spacers 318 are preferred in the present invention because of the hermetic seal, any other suitable insulating layer such a deposit oxide can be used, if desired. A silicon nitride layer 314 can be formed by a low pressure chemical vapor deposition (LPCVD) process by reacting ammonia (NH3) and dichlorosilane (DCS) at a pressure of approximately 10 pascals and at a temperature of approximately 800° C. A silicon nitride film can be anisotropically etched using chemistry comprising C2F6 and a power of approximately 200 watts.
Next, as shown in FIG. 3E, a silicon or silicon alloy film 320 is selectively deposited onto intrinsic silicon film 308 adjacent to the outside edges of sidewall spacer 318. Silicon or silicon alloy film 320 is selectively deposited so that it forms only on exposed silicon, such as intrinsic silicon 308 and the top of polysilicon film 314. Silicon or silicon alloy is not deposited onto thin spacers 318. Thin spacers 318 electrically isolate silicon or silicon alloy film from gate electrode 316. By forming silicon or silicon alloy film 320 onto intrinsic silicon film 308, silicon or silicon alloy 320 is formed above the surface on which gate dielectric layer 310 is formed, a "raised" tip is formed which increases the conductivity of the tip which in turn improves the device performance. By forming a raised tip in the present invention, shallow tips can be formed and good punchthrough characteristics obtained. The silicon or silicon alloy 320 is doped with p type impurities for a PMOS device or with n type impurities for an NMOS device to a concentration level between lxl018/cm3 to 5xl020/cm3 with a concentration of approximately lxl020/cm3 being preferred. The silicon or silicon alloy can be insitu doped during deposition or subsequently doped by ion implantation. In an embodiment of the present invention, the silicon or silicon alloy 320 is epitaxial silicon germanium and is insitu doped.
According to an embodiment of the present invention, silicon or silicon alloy film 320 is preferably a silicon germanium semiconductor alloy with germanium comprising approximately 10-50% of the alloy. A silicon germanium semiconductor alloy can be formed by decomposition of approximately 20 seem of dichlorosilane, approximately 130-180 seem of 1% hydrogen diluted germanium (GeH4) at a temperature of between 600-800° C. with 700° C. being preferred and a power of approximately 20 torrs. If desired, a p type dopant source or an n type dopant source may be included into the gas mix to insitu dope the silicon alloy during deposition. Alternatively, the silicon or silicon alloy can be ion-implanted to the desired conductivity after the deposition of the silicon or silicon alloy film. In order to increase the selectivity of the deposition process, approximately 25-50 seem of HCo can be added to the gas composition, if desired.
A silicon germanium alloy is preferred because it exhibits good selectivity to silicon during deposition. Additionally, such silicon germanium alloy exhibits many microscopic