CMOS INPUT BUFFER RECEIVER CIRCUIT
WITH ULTRA STABLE SWLTCHPOINT
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to input buffer circuits for CMOS devices. More particularly, the present invention relates to TTL to CMOS or CMOS to CMOS input buffer receivers having extremely stable switchpoints which are insensitive to process and temperature variations.
2. Description of the Prior Art
Input buffers for TTL to CMOS signals are classified in International Class H03K 19/094 and U.S. Class 307, Sub-Classes 475, 296, and 297.
One of the problems with normal or conventional CMOS input buffer receivers is that their switchpoints are centered about a point which is one-half the supply of voltage (approximately 2.5 volts, Vd£>/2). However, the input signal to the CMOS device often does not swing around Vdd/2 but swings about or around 1.4 volts as in the case of TTL inputs. When the driver input is TTL, the switchpoint of the input CMOS buffer receiver needs to be lowered so that it is centered around 1.4 volts.
It would seem that recognition of this problem would result in being able to provide a CHOS receiver having its threshold switchpoint centered about the mid-point of the voltage excursion of the incoming driver signal. It has been suggested in the prior art that CMOS receivers be designed so that the receiver logic element has its normal switchpoint designed for matching the midpoint of the input drivers voltage excursion. However, the switchpoint for the on-chip CMOS receiver buffers varies with the process fabrication (channel length and threshold characteristics vary); power supply (variations of ± 10% are common), and temperature changes (minus 55 degrees C. to 125 degrees C. as occurs in military specifications). As a result of these variations the switchpoint of the CMOS devices typically varies from 1 volt to 1.8 volts. The mid-point of an incoming TTL signal or CMOS signal can be tied to a reference voltage, but the switchpoint of the CMOS receiver buffer provides a moving target.
U.S. Pat. No. 4,471,242 teaches a TTL to CMOS input buffer. The principle of operation of this circuit is to provide a reference voltage generator between the Vdd voltage used for the CMOS chip and the Vdd voltage used for the input buffer driver. The reference voltage generator drops the Vdd input buffer voltage to a voltage at or slightly above the high voltage level of the incoming TTL signal. The net effect of lowering the effective supply voltage is to eliminate the steady state current flowing through the input driver pair when the TTL input voltage is in the high state. This has nothing whatsoever to do with stabilizing the input voltage switchpoint.
The aforementioned problems become acute when the incoming driver signal is supplied to the CMOS buffer receiver over a transmission line. The resultant voltage levels at the input of the CMOS receiver which is at the end of a transmission line appear as a staircase wave form as opposed to a smooth, sharp, and fast voltage transition.
It has been suggested in the prior art that enlarging the driver to supply more current would result in a sufficient voltage swing to effect switching of the
CMOS receiver on the first or second staircase wave form, however, the larger current driver also requires more device area and larger base delays accompanied by an increase in noise currents on the CMOS chips.
5 The larger the number of receivers to be driven, the more severe the noise problem becomes when a larger driving current is necessary.
It would be extremely desirable to provide a CMOS input buffer receiver which has an ultra stable and pre
10 dictable switchpoint.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide a new and improved on-chip CMOS input 15 buffer receiver.
It is another principal object of the present invention to provide a CMOS buffer receiver which reduces transmission line bus delays.
It is another principal object of the present invention 20 to reduce the simultaneous switching noise from the input signal driving device.
It is another principal object of the present invention to provide a novel input buffer receiver having fewer 25 transitors for a circuit which solves the bus delay and transmission problems.
It is a general object of the present invention to provide a CMOS buffer receiver having improved noise immunity.
3Q It is another object of the present invention to provide a novel input buffer receiver having smaller transistors devices which results in higher density devices.
It is another general object of the present invention to provide an input buffer receiver having faster switching
35 time than prior arts circuits.
According to these and other objects of the present invention, there is provided a pair of reference voltage generators which are coupled to a compensating network which detects the variations in wafer fabrication,
40 supply voltage and temperature. The output of the compensating network is coupled to one input of a stabilized CMOS input converter whose output voltage and input switchpoint track or follow the pair of reference voltages of the reference voltage generators resulting in a
45 stable input converter switchpoint.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of a basic prior art TTL to CMOS input converter; 50 FIG. 2 is a schematic block diagram of a basic prior art CMOS to CMOS input converter;
FIG. 3 is a schematic block diagram of an improved prior art TTL to CMOS input converter; FIG. 4 is a schematic block diagram showing the 55 transistor configuration for operation of the input converter of FIG. 3;
FIG. 5 is a schematic representation showing transmission line loading as occurs on printed circuit boards; FIG. 6 is a schematic wave form diagram showing 60 typical delays that occur on the transmission line shown in FIG. 5;
FIG. 7 is a schematic block diagram of the preferred embodiment input buffer receiver;
FIG. 8 is a schematic block diagram of one of the 65 reference voltage generators employed in FIG. 7;
FIG. 9 is a schematic block diagram of a second reference voltage generator of the type employed in FIG. 7;