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INTELLIGENT DIGITAL SIGNAL HITLESS
CROSS-REFERENCE TO RELATED
This application is a continuation of application Ser. No. 08/044,348, filed Apr. 7, 1993, now abandoned.
This application describes material that was described and claimed in my co-pending United States patent application 10 entitled "Error Correction and Channel Restoration Apparatus for DS1 Digital Links" filed simultaneously herewith, assigned Ser. No. 08/044,327, now U.S. Pat. No. 5,506,956 and which has been assigned to the present assignee hereof.
FIELD OF THE INVENTION
This invention relates generally to digital communication networks and, more specifically, to protection circuitry and a concomitant methodology for providing substantially 20 error-free communication links in support of DS1 and higher speed services.
BACKGROUND OF THE INVENTION
Since the introduction of digital transmission into telecommunications networks in the 1960's, a sophisticated digital transmission network hierarchy has evolved based on the so-called digital signal at the first level, that is, DS1. It is necessary to trace pertinent aspects of this evolution so as 3Q to provide a context for presenting and discussing the prior art as well as to set forth with specificity the limitations of the prior art.
When first introduced into telecommunications networks, digital transmission was based on the propagation of digital 35 signals in the now well-known Tl carrier format. In this format, 24 voice-frequency signals are sampled and then multiplexed into a digital bit stream, thereby forming 24 autonomous voice-frequency channels. All 24 channels are grouped together to form a 192-bit data group. For synchro- 40 nization, every group of 192 bits is preceded by a framing bit; these 193 bits comprise a Tl frame. Each voicefrequency channel is allocated 8 bits in the 193-bit frame; these 8 bits represent one encoded sample of a particular voice signal as well as signalling information. Thus, a Tl 45 frame is composed of 192 bits of information and one overhead framing bit. Consequently, since the sampling rate of the voice-frequency signal is 8 kHz, meaning each encoded sample of the voice-frequency signal must be updated 8000 times a second, the transmission rate of the Tl 50 system is 1.544 Mbits/sec. To support two-way communication, two digital bit streams are generated—one for each direction of transmission. Each bit stream is transmitted over a corresponding unidirectional link typically composed of a wire-pair cable and interposed repeaters so that a complete 55 Tl system utilizes two wire-pair cables.
The original Tl terminals used at the ends of the wire-pair span to multiplex the 24 voice-frequency signals were designated Dl channel banks. Dl frame format used every 193rd bit totally for frame synchronization. Seven bits in 60 each frame were used for customer data with one additional bit being used for signalling. As advances in technology evolved, other framing formats were devised to improve the performance of the underlying Tl system. For example, the D2 frame format introduced the so-called superframe 65 wherein 12 contiguous Tl frames having a unique 193rd bit sequence were repeated once every 12 frames. The D2
framing format also introduced "robbed bit" signalling. In the D2 framing format, only one bit in frames 6 and 12 was used for signalling. The remaining bits were allocated to encode customer voice. The use of all eight bits for voice in 10 out of 12 frames resulted in substantial improvement of voice transmission quality compared to the Dl framing format. DID, which followed D2, made the superframe concept "backward compatible" with the original Dl type channel banks. The last frame format to utilize a 12-frame superframe concept was the D4 frame format. The most recent framing format, designated the Extended Superframe Format (ESF), dramatically improves the capabilities of Tl systems and affords the opportunity to perform diagnostics on working Tl systems without disrupting communications. Because of technology improvements, fewer bites are now required to maintain frame synchronization as compared to the D4 banks. In ESF, a 24-frame sequence is used for framing, in-service end-to-end performance monitoring, and facility data link (FDL) that allows communication on the Tl link independent of the customer data traffic. The fundamentals of ESF will be discussed in more detail shortly after the types of errors that arise in a Tl system are discussed.
Using the Tl format as a basic building block, a hierarchy of digital networks has evolved in North America. For example, in addition to Tl which supports the DS1 hierarchy level, there are the T2 and T3 formats which operate at 6.312 Mbits/second and 44.736 Mbits/second, respectively. T2 and T3 formats support the DS2 and DS3 hierarchy levels. A T2 format has four times the capacity of a Tl format or 96 voice-frequency signals. A T3 format has 28 times the capacity of a Tl format. Thus, the notion of digital hierarchy should be distinguished from the underlying physical transmission systems supporting the hierarchy. For example, the first digital hierarchical level, DS1, is implemented with the 1.544 Mbit/sec. Today, Tl transmission systems deploy either the latest D4 frame format or the ESF format. The service provided by the first hierarchical level is generally referred to as DS1 service.
A Tl digital bit stream, that is, a stream of Tl frames, must follow certain propagation rales. For instance, when bits of the Tl signal are propagated over the communication medium, one rule requires that each "1" bit must correspond to a pulse having a polarity opposite to the polarity of the previous "1" bit—this format generates a bipolar signal composed of a stream having alternating positive and negative electrical pulses. For each "0" bit, no electrical pulse is propagated. Such a bipolar signal leads to spectral efficiency, and also results in a frequency spectrum lacking a DC component, thereby requiring only AC-coupled circuitry. Another rule requires that, to maintain signal synchronization, no more than a certain number of "0" bits can be transmitted consecutively. A logic error occurs if a "1" bit appears where a "0" bit should occur, and vice versa. A format error occurs when there is a violation in the bipolar nature of the pulse stream, or an error in the framing bits, or excessive "0" bits occur.
For all frame formats existing prior to the introduction of the ESF, testing of in-service links was limited to checking for format errors. The basic assumption was that any logic error caused a format error. But it can be readily shown that only certain logic errors cause format errors. For instance, if two consecutive "1" pulses in the bit stream, say a positive pulse followed by a negative pulse, are converted to "0" bits, then no format errors occur since there are no bipolar violations. However, two logic errors have occurred. In addition, a typical Tl circuit is likely to contain several
bipolar signal sources. For example, a higher order M13 multiplexer puts several Tl systems into a fiber link. The Tl ports on the M13 multiplexer are a source for bipolar signals and must "correct" any bipolar violations from other parts of the transmission path because fiber does not carry bipolar 5 signals. As a result, a channel bank at the other end of the Tl link can monitor bipolar violations, but this will reveal only errors that occurred in the last leg of the path from the last M13 multiplexer (i.e., bipolar pulse source) to the channel bank. Thus, end-to-end error performance monitoring cannot be provided with D4 framing format. Obviously there was a need to develop a technique which could accurately detect end-to-end DS1 performance of an in-service Tl system.
This aforementioned need was satisfied by the development of the ESF concept. With respect to the principles of 15 ESF, each superframe is defined as encompassing 24 Tl-type frames, so each superframe is composed of 24x193=4632 bits, including 4608 information carrying payload bits and 24 synchronization bits. The framing bit of a conventional Tl system, i.e., the 193rd bit, is conveyed at 20 an effective rate of 8000 bps. Accordingly, the 24 bit positions in the superframe occupied by the 193rd bit in each of the 24 underlying frames also are conveyed at the same rate of 8000 bps.
However, because of the aforementioned advances in technology, it is only necessary to use six of the 24 bits for actual superframe synchronization. Thus, if the 24 bits occupied by the 193rd bit are extracted and arranged serially to create a framing bit segment, then the convention is that 3Q superframe synchronization bits are conveyed by every fourth bit in the framing bit segment, that is, in the superframe synchronization sub-segment. The superframe synchronization bits have a fixed bit pattern which convention- , ally has been set at 001011. It is important to reiterate at this 35 point that the framing bit segment is actually an overhead portion of the ESF superframe (that is, each of the other 192 bit positions in each of the 24 frames defining the superframe is used to carry user information data and signalling; this data is unaffected by what is being conveyed in the 4Q framing bit segment).
The remaining 18 bits in the frame segment are partitioned into a check sub-segment of 6 bits and a facility data link (FDL) sub-segment of 12 bits. The check sub-segment is of particular relevance to the present invention. 45
As indicated above, the primary reason for devising the ESF technique was to enable Tl users/suppliers to accurately measure end-to-end error performance of a Tl system while the system is on-line, that is, without interrupting the propagation of the Tl digital streams. This is accomplished 50 by applying a coding theory technique, called Cyclic Redundancy Codes (CRC), to each ESF. With the CRC technique, all 4608 payload bits in each complete ESF superframe can be checked for logic errors. In essence, for the particular CRC technique used in ESF (called CRC-6), six bits are 55 generated for each ESF superframe; these six bits are indicative of the actual 4632 bits comprising a given superframe. Computation of the six check bits involves nothing more than division and modulo-2 arithmetic. For example, assume that the ESF bit stream, rather than being 4632 bits 60 long, is 10 bits long and the pattern is 1010101010, which has a decimal equivalent of 682. This decimal equivalent is divided by 64 (26=64, that is, 6 bits are dedicated to the check sub-segment), resulting in a quotient of 10 and a remainder of 42. The quotient is ignored, and the six-bit 65 binary equivalent of the remainder, i.e., 42, namely, 101010, are the check bits transmitted in the next superframe.
To visualize the flow of bits in a temporal sequence, consider a time sequence of two ESF superframes designated the first ESF superframe and the second ESF superframe which follows the first ESF superframe in time. The six check bits computed for the first ESF superframe are entered into the check sub-segment of the second ESF superframe and transmitted to the receiving end of the Tl system. At the receiving end, the CRC-6 of the first ESF superframe is dynamically computed. Obviously all 4632 bits of the first ESF superframe are needed to compute the check bits, so the CRC-6 cannot be completed until all bits arrive at the receiving end. Once computed, the CRC-6 check bits can then be compared to the check sub-segment arriving in the second ESF superframe. If there is a match, then it is concluded with a high degree of confidence that there were no errors in the first superframe. If there is no match, this is normally taken to mean that at least one error occurred in the first superframe. (Of course, the check bits in the second superframe may have been corrupted, but the probability of this occurring, i.e., errors in the six bit positions, is much less than the occurrence of errors in 4608 payload bit positions.) The unfolding nature of error checking for the general case is now readily discernible: the CRC-6 bits of a given superframe are transmitted in the check sub-segment of the next superframe following the given superframe.
Representative of prior art devices and equipment which exploit the capabilities of error detection using CRC-6 with ESF superframes is the Automatic Protection Logic Switch (APLS) available from the Verilink Corporation, San Jose, Calif. The ALPS checks a working Tl line for logic errors, and when a preset Bit Error Rate (BER) threshold is reached, or an active link outage is detected, traffic is automatically switched from the active Tl link to a standby Tl link. Such an arrangement is deficient, however, because the protection link is activated only after errors occur and the BER threshold is reached. Consequently, all errors which occurred in the active link prior to the activation of the protection link reach the end-user. Also, a difference typically occurs in the propagation delay between the active and protection links. When the protection link is activated, the end-user will encounter a "hit" in the data stream; this "hit" is usually in the form of a gap in the data stream or repeated segment in the data stream.
There is no teaching or suggestion in the art, of synchronized digital transmission, of an arrangement and concomitant methodology which utilizes the protection DS1 link to correct errors in the active DS1 link and to synchronize active and protection DS1 links to achieve "hitless" protection switching when the active DS1 link fails—as distinct from the sequence in the prior art of error-detection first, then subsequent protection switching to the alternate facility only after a period of delay. Furthermore, there is no teaching or suggestion in the art treating higher speed systems such as DS3 which also achieve "hitless" protection switching.
SUMMARY OF THE INVENTION
These limitations and other shortcomings and deficiencies are obviated, in accordance with the present invention, by advantageously transmitting the same digital signal data streams (e.g. DS1 and DS3) over two parallel communication links, and by selecting in a receiver, on a superframe basis, the superframe conveying error-free data prior to delivery to an end user.
In accordance with the broad aspect of the present invention, receiver circuitry is arranged to interconnect on a superframe basis an output port to: either a first autonomous communication link which propagates a stream of superframes in Extended Superframe Format (ESF); or a second 5 autonomous link which propagates the same stream of superframes as the first link, wherein the interconnection is controlled in response to error calculations on the two links. Because the links generally have different propagation delays, the data stream which arrives first at the receiver 10 because of a shorter propagation time on one of the links is delayed in order to align the data streams arriving over the links. Both information and framing bits (i.e., all 193 bits) are utilized to align the first ESF superframes and second ESF superframes. The first and second ESF superframes are 15 separately stored in first and second buffers. In parallel with storing the superframes in the buffers, the superframes are processed to detect the presence or absence of errors in each of the first ESF superframes or presence or absence of errors in each of the second ESF superframes using the CRC-6 20 check data contained in the ESF superframes and CRC-6 calculations on the first and second ESF superframes, respectively. Finally, the output port, which is initially connected to, say, the first link, is switched to the second buffer to select an error-free ESF superframe upon the 25 detection of errors in the ESF superframe in the first link, and the absence of errors in the ESF superframe in the second link to select and thereby provide error-free ESF superframes to the output port. Because the superframes are buffered during error calculations, it is possible to switch 30 "hitlessly" to the link having an error-free condition during each ESF superframe interval. If both links have errors in a given superframe, errors cannot be corrected. In this case, the receiver selects the ESF superframe from the link which has had a better recent error performance. 35
To achieve hitless protection switching in higher speed systems, such as DS3 systems, these systems may also be arranged through use of my invention, with check data bits in an overhead data stream and substantially identical buffering along with check data computation, all as broadly 40 described above.
BRIEF DESCRIPTION OF THE DRAWINGS
The organization and operation of this invention can be clearly understood from considering the following detailed description in conjunction with the accompanying drawings in which:
FIG. 1 illustrates, in high-level block diagram form, a 50 prior art network providing DS1 service using a single Tl link and channel service units (CSU's) to interface a Tl facility;
FIG. 2 illustrates, in high-level block diagram form, a prior art network providing DS1 service using both active 55 and backup Tl links;
FIG. 3 is a block diagram of a APLS unit suitable for deployment in the system of FIG. 2;
FIG. 4 is a high-level block diagram of one illustrative 6Q transmitter-receiver pair, in accordance with the present invention, for a system having route diversity;
FIG. 5 is an illustrative embodiment of the ESF superframe selector of FIG. 4; and
FIG. 6 is a block diagram of an illustrative embodiment 65 of a receiver, in accordance with the present invention, for use in a high speed, synchronous digital signal system.
To place the detailed description of the present invention in perspective and thereby highlight the departure from the art as disclosed and claimed herein, it is both instructive and informative to first gain a basic understanding of the telecommunications environment in which the present invention operates by presenting certain foundational principles concerning a conventional DS1 service. Accordingly, the initial part of this detailed description discusses pertinent specifics of the prior art. This approach has the advantage of introducing notation and terminology which will aid in elucidating the various detailed aspects of the present invention. After this description, the circuitry aspects of the present invention, as well as the concomitant methodology, are presented with specificity.
As depicted in high-level block diagram form in FIG. 1, prior art network 100 connecting Digital Transmission Equipment 110 at End-A (DTE-A) with Digital Transmission Equipment 150 at End-B (DTE-B) includes a cascade of: Channel Service Unit (CSU) with D4/ESF (Extended Superframe Format) converter 120; single Tl link 130; and Channel Service Unit (CSU) with D4/ESF converter 140. Each CSU 120 or 140 is a device which forms an interface between a public network (Tl link) and an end-user to mitigate such disturbances as lightning transients and enduser equipment power outages. Typically, the D4/ESF converter is an integral part of the CSU. Network 100 represents one of the basic ways of implementing ESF in the Tl network today, namely, by retrofitting an existing Tl system with a conversion device that converts a digital stream having a D4 frame format to a digital stream implementing ESF. The CSU is such a conversion device. Framing formats Dl, D2, DID, and D3 are no longer used in the industry. On one side of a CSU, say CSU 120, the digital stream transceived by DTE-A 110 is shown as having "D4 Framing". On the other side of CSU 120, the digital stream is in ESF form. The framing re-formatting is transparent to Tl link 130; this link typically comprises two wire-pair cables and repeaters.
Another prior art arrangement, utilized by many service providers, improves reliability of network 100 by utilizing two DS1 links (routes) and a DS1 switch called Automatic Line Protection Switch (ALPS). However, the improved system, while providing higher reliability DS1 service, still allows errors to reach an end-user. To explain the improved system, reference is initially made to FIG. 2. Prior art network 200 connecting Digital Transmission Equipment 110 at End-A (DTE-A) with Digital Transmission Equipment 150 at End-B (DTE-B) includes a cascade of: ALPS 210; two parallel DS1 routes connected to APLS 210, wherein the first DS1 route is composed of CSU 221, Tl link 231, and CSU 241, and wherein the second DS1 route is composed of CSU 222, Tl link 232, and CSU 242; and APLS 250 which connects the two parallel DS1 routes. One Tl link, (e.g., link 231), is an active link, whereas the other link (e.g., here link 232) is a standby link. As the names imply, the active link is the link actually delivering the digital stream between APLSs 210 and 250, whereas the standby link, although propagating the digital stream, does not deliver its stream to the APLSs for processing. However, the standby link may readily deliver the digital data stream in place of the active link whenever necessary. To exemplify the interaction between the active and standby links, reference is now made to FIG. 3.