ASYNCHRONOUS TIME DIVISION SWITCHING ARRANGEMENT AND A METHOD OF OPERATING SAME
FIELD OF THE INVENTION
The present invention relates to asynchronous time division switching arrangement and a method of operating the same.
In the field of broadband telecommunications networks a requirement has arisen for a switching system that can switch bursty or deterministic digital data streams of differing data rates with many origins to many differing destinations.
DESCRIPTION OF THE PRIOR ART
A method of achieving this goal has been employed world wide in the use of asynchronous time division multiplexing, where data is transmitted in packets. These packets contain many bytes of data, for example 32, together with a header of typically 3 or 4 bytes containing a virtual circuit number unique to that connection on that line, as well as check bytes, etc. The need has arisen therefore, for a switch that can switch these packets of data for any input line to any output line and allocate a new virtual circuit number.
Several solutions have already been made to this problem but all require large amounts of a RAM, or extra hardware, which limits the maximum switch size that can be accommodated on an integrated circuit. The closest solution to this problem has been a switch developed by CNET. This switch does not use the self-routing approach and hence requires a large RAM for the translation of the virtual circuit number to be incorporated in each switch. The present invention only requires one translation at the input to the switch structure which may use one or a plurality of stages of switching, each stage using one or more switching arrangements as described in the invention, and where one or more 'routing digits' are added to the front of the packet which together define the path to be used through the switch structure and which are removed at the output from the switch structure. The CNET switch employs a paradiagonal conversion of the inputs to produce interleaved bytes of data for presentation to the data RAM. This requires a faster access RAM than in the present invention where the wide serial to parallel shift registers allow more time for the interleaving of the RAM accesses using time multiplexing. The CNET switch uses separate blocks of memory for each of the input queues, whereas a shared memory for the queues enables a reduction to be made in the RAM size, and the use of output rather than input queues eliminates the possibility of cells being blocked. In a switching arrangement more than one input may address the same output at the same time and hence the need for a queue at each output since a single output may only transmit one packet at a time. In a switching arrangement with an equal number of inputs and outputs (the most usual case in practice) if more than one input addresses the same output at the same time, thus increasing the length of the queue at the output, there must be other outputs which are not addressed at that time thus their queues must shorten. If a common memory is shared between all the output queues on the arrangement then the memory capacity is used more efficiently since memory capacity can be allocated to where it is most needed. The result is that, with a shared memory, a smaller total
memory capacity is needed to achieve the same probability of loss of packets due to memory overflow. It can be shown that, with more than one output served, the required total memory capacity is approximately halved
5 for the same probability of lost packets.
A second advantage to a shared memory is that if the arrangement is used to concentrate a number of inputs onto a smaller number of outputs using a standard arrangement equipped with a larger number of outputs,
10 for example equal to the number of inputs, the memory which would have been allocated to unused outputs in the case of separate output queues becomes available, with shared memory, for use on the outputs which are used.
SUMMARY OF THE INVENTION
Accordingly, an aim of the present invention is to provide an asynchronous time division multiplex switching arrangement which provides for a common
20 memory which is shared by all output queues, and which overcomes the above mentioned problem, and which can be implemented using silicon technology, for example integrated circuit technology, making efficient
25 use of the chip area.
The optimum position for the queues is at the output ports of the arrangement, however an output queue may be simultaneously addressed by all the input ports of the arrangement thus the input bandwidth of the
jQ queue must be N times the input port rate, where N is the number of input ports. Since the access cycle time of memory is relatively long, the queue memory must use a very large word length in order to cyclically access all the input ports in the required time and this also implies
35 serial to parallel converters at each input and parallel to serial converters at each output. The invention uses memory words which are a fraction 'k' of a packet long, where 'k' is an even number. Use of adjacent odd and even pairs of the 'k' segments permits swing buffering
40 of the input and output ports, one segment being held static in the input serial to parallel converter whilst the following segment is being received and similarly, one segment being parallel loaded to the output parallel to serial converter whilst the previous segment is being
45 transmitted. Typical values of 'k' are 2 or 4, the choice depending upon memory speed and the geometry of the device. In this way enough time is provided to allow all of the inputs to be entered into a common queue memory. The highly parallel internal operation of the device
50 is embodied in the topology which allows a very efficient use of silicon area in an integrated device.
STATEMENT OF THE OBJECT OF THE
55 According to the present invention there is provided an asynchronous time division multiplex switching arrangement comprising a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the
60 packets of data to parallel form, a random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in-first-out output queue at the tail, and the address at the head of the
65 queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to a required output.