Asynchronous time division switching arrangement and a method of operating same

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ASYNCHRONOUS TIME DIVISION SWITCHING ARRANGEMENT AND A METHOD OF OPERATING SAME

FIELD OF THE INVENTION

The present invention relates to asynchronous time division switching arrangement and a method of operating the same.

In the field of broadband telecommunications networks a requirement has arisen for a switching system that can switch bursty or deterministic digital data streams of differing data rates with many origins to many differing destinations.

DESCRIPTION OF THE PRIOR ART

A method of achieving this goal has been employed world wide in the use of asynchronous time division multiplexing, where data is transmitted in packets. These packets contain many bytes of data, for example 32, together with a header of typically 3 or 4 bytes containing a virtual circuit number unique to that connection on that line, as well as check bytes, etc. The need has arisen therefore, for a switch that can switch these packets of data for any input line to any output line and allocate a new virtual circuit number.

Several solutions have already been made to this problem but all require large amounts of a RAM, or extra hardware, which limits the maximum switch size that can be accommodated on an integrated circuit. The closest solution to this problem has been a switch developed by CNET. This switch does not use the self-routing approach and hence requires a large RAM for the translation of the virtual circuit number to be incorporated in each switch. The present invention only requires one translation at the input to the switch structure which may use one or a plurality of stages of switching, each stage using one or more switching arrangements as described in the invention, and where one or more 'routing digits' are added to the front of the packet which together define the path to be used through the switch structure and which are removed at the output from the switch structure. The CNET switch employs a paradiagonal conversion of the inputs to produce interleaved bytes of data for presentation to the data RAM. This requires a faster access RAM than in the present invention where the wide serial to parallel shift registers allow more time for the interleaving of the RAM accesses using time multiplexing. The CNET switch uses separate blocks of memory for each of the input queues, whereas a shared memory for the queues enables a reduction to be made in the RAM size, and the use of output rather than input queues eliminates the possibility of cells being blocked. In a switching arrangement more than one input may address the same output at the same time and hence the need for a queue at each output since a single output may only transmit one packet at a time. In a switching arrangement with an equal number of inputs and outputs (the most usual case in practice) if more than one input addresses the same output at the same time, thus increasing the length of the queue at the output, there must be other outputs which are not addressed at that time thus their queues must shorten. If a common memory is shared between all the output queues on the arrangement then the memory capacity is used more efficiently since memory capacity can be allocated to where it is most needed. The result is that, with a shared memory, a smaller total

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memory capacity is needed to achieve the same probability of loss of packets due to memory overflow. It can be shown that, with more than one output served, the required total memory capacity is approximately halved

5 for the same probability of lost packets.

A second advantage to a shared memory is that if the arrangement is used to concentrate a number of inputs onto a smaller number of outputs using a standard arrangement equipped with a larger number of outputs,

10 for example equal to the number of inputs, the memory which would have been allocated to unused outputs in the case of separate output queues becomes available, with shared memory, for use on the outputs which are used.

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SUMMARY OF THE INVENTION

Accordingly, an aim of the present invention is to provide an asynchronous time division multiplex switching arrangement which provides for a common

20 memory which is shared by all output queues, and which overcomes the above mentioned problem, and which can be implemented using silicon technology, for example integrated circuit technology, making efficient

25 use of the chip area.

The optimum position for the queues is at the output ports of the arrangement, however an output queue may be simultaneously addressed by all the input ports of the arrangement thus the input bandwidth of the

jQ queue must be N times the input port rate, where N is the number of input ports. Since the access cycle time of memory is relatively long, the queue memory must use a very large word length in order to cyclically access all the input ports in the required time and this also implies

35 serial to parallel converters at each input and parallel to serial converters at each output. The invention uses memory words which are a fraction 'k' of a packet long, where 'k' is an even number. Use of adjacent odd and even pairs of the 'k' segments permits swing buffering

40 of the input and output ports, one segment being held static in the input serial to parallel converter whilst the following segment is being received and similarly, one segment being parallel loaded to the output parallel to serial converter whilst the previous segment is being

45 transmitted. Typical values of 'k' are 2 or 4, the choice depending upon memory speed and the geometry of the device. In this way enough time is provided to allow all of the inputs to be entered into a common queue memory. The highly parallel internal operation of the device

50 is embodied in the topology which allows a very efficient use of silicon area in an integrated device.

STATEMENT OF THE OBJECT OF THE
INVENTION

55 According to the present invention there is provided an asynchronous time division multiplex switching arrangement comprising a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the

60 packets of data to parallel form, a random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in-first-out output queue at the tail, and the address at the head of the

65 queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to a required output.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the present invention will now be described with the reference to accompanying drawings wherein the value of 'k' is 2 and in which, 5

FIG. 1 shows a block diagram of one way of implementing the invention,

FIG. 2 shows input serial to parallel and output parallel to serial converters as used in FIG. 1,

FIG. 3 shows a diagram of data flow, 10

FIG. 4 shows a memory map,

FIG. 5 shows a 16 by 16 shared queue asynchronous time division multiplex switch, and,

FIG. 6 shows a typical switch structure using switching arrangements according to the present invention. 15

DESCRIPTION OF THE PREFERRED
EMBODIMENT

Referring to FIG. 1, a central core of an eight input, eight output asynchronous time division multiplex 20 (ATD) switch is shown which operates at a data rate of approximately 160 Mbit/s, which for this simplified case, has a dedicated section of the memory allocated to each output queue. The system consists principally of an 8 input, 152 bit serial to parallel converter 1, a 38 kbit 25 RAM 2 which implements the 16 packet FIFO queue associated with each output line, and an eight output parallel to serial converter 3. A queue processor 4 calculates a read and write address associated with each output queue while a register file 5 is employed to store 30 the read and write address pointers, and the queue full/empty flags. A timing/synchronisation block 6 generates the timing signal required by the ATD logic. Signal PUR represents a reset signal when the arrangement is powered up. The serial to parallel converter 1 is shown 35 receiving data input bits To to T151 at a rate of 160 Mbit/s from ports LIo to LI7. The serial parallel converter 1 is controlled by a 'walking one' sequencer 7 and an address counter 11. Similarly the parallel to serial converter 3 is also controlled by a 'walking one' se- 40 quencer 8, and an address counter 12. The counters generates a 3 bit coded data signal for timing purposes. The data is shown leaving the parallel to serial converter 3 via output lines LOoto LO7 at a data rate of 160 Mbit/s. 45

The 1st bit of the 1st half of a packet is reserved for a synchronisation bit. The 2nd and 3rd bits are used to indicate whether the current slot at the input is carrying a packet or is unused, the code 00 is used to indicate the unused state and will set a flag in the input address 50 register 10 which will result in the subsequent attempt to write to an output queue being aborted. The bits immediately following the 3rd bit will carry routing digits, the portion of the packet allocated to the routing field is arbitrary provided that it does not overflow into 55 the 2nd half of the packet. The position of the routing digit used by the device is in the bits immediately preceding the termination of the externally supplied Clock Slot pulse. The 1st half of the packet is fed to four bits of the input address register 10, these bits are connected 60 as a shift register with a clock which is enabled by the presence of the Slot Clock pulse; thus these four register bits will hold the last four bits received prior to the termination of the Slot Clock pulse during receipt of the 2nd half of the packet. 65

The queue processor 4 is controlled by a 'walking one' sequencer 9 which in turn is controlled by the timing synchronisation block 6. The serial to parallel

converter 1 also extracts input address register information which is fed to an input address register 10. The register 10 is controlled by a counter 11, and the address information is passed to the queue processor 4. The empty flag is used by the queue processor to abort write access to the RAM 2.

For an ATD packet size of 304 bits, all inputs must be synchronised to 304 bit slots on the bearers and capable of being switched to any outgoing line number. If the particular output queue is full the incoming ATD cell routed to this queue is discarded. Under queue empty conditions the output D (diagnostic) and busy/free bits (B/F), as shown in FIG. 2, within the cell are set to zero while all other positions except for bit O, contain undefined data. Bit O, designated S is a synchronisation bit carrying a slot sync signal which acts as a local reference for timing purposes.

The selection of 304 bits for the packet length is made up as follows, 32 bytes of data, a 3 byte header and a 3 byte header internal to the switch structure which includes S, D and B/F bits and a 15 bit routing address.

Each input ATD cell of 304 bits of data must be stored in the addressed output FIFO queue. The switch has an internal cycle time of 100 ns, which is the time available for one memory read and one memory write operation. The input serial to parallel converter shown as 1 in FIG. 1 is shown in more detail in FIG. 2. Also the parallel to serial converter 3 is shown in more detail in FIG. 2. The serial to parallel converter shown in FIG. 2 consists of two 152 bit latches (A and B) at each input and a 152 bit 'walking one''sequencer 15 common to all inputs, the use of a 'walking one' sequencer together with latches reduces the power dissipation in a CMOS implementation by at least an order of magnitude over a shift register solution at high data rates.

During the first half period of an input ATD cell, data is stored in the A register, incoming bit 0 being stored in latch bit position 0, and incoming bit 151 being stored in latch bit position 151. The 'walking one' sequencer 15 cyclically selects each latch in turn to store incoming data thus only a few transistors are changing state, and hence consuming power, at each clock cycle. While the A register is being filled, the data in the B register is static and avaiable to be written into the RAM for the output specified by the identified routing digit. When the A register is full, the incoming data switches to the B register, and the B register is sequentially filled with the incoming second half of the ATD cell data. During this period the A register is static and available to be written into the RAM. Similarly the operation of the parallel to serial converter 3, in FIG. 1 and shown in FIG. 2 as register A' and register B', is similar to that as described in relation to registers A and B.

Each input such as LIo for example, is fed via a standard logic circuit 13, which directs the data to the appropriate half of the serial to parallel converter A, B. The data is gated into the respective bit position of the serial to parallel converter A, B by way of a respective gate 14 for example, which in turn is controlled by the 'walking one' sequencer 15.

The output from the respective parallel to serial converter A', B' is fed via a 2 to 1 multiplexer circuit 16 and fed out via a toggle 17 and inverter 18 to an output buffer 19. The output buffer 19 outputs the data on line LO0.

FIG. 3 shows the data flow throughout the ATD switch. It can be seen that there is a minimum of 304