METHOD AND APPARATUS FOR SUMMARY REDUCING POWER CONSUMPTION DUE
TO GATE LEAKAGE DURING SLEEP MODE One embodiment of the present invention provides a
system that achieves low gate leakage current in an inte
BACKGROUND 5 grated circuit during sleep mode. Upon entering sleep mode,
the system reduces the power supply voltage applied to the
1 r- u c .t. T integrated circuit to a low voltage level, wherein the low
1. Meld oi the Invention , , , . , , •, , , ,
voltage level is low enough to provide a low gate leakage
The present invention relates to the design of CMOS current, but is high enough to maintain state in the integrated
integrated circuits. More specifically, the present invention 10 circuit
relates to a method and an apparatus for reducing power In a variation 0f this embodiment, the low voltage level is
consumption due to gate leakage current during sleep mode so iow that the integrated circuit cannot perform computa
in CMOS integrated circuits. tion operations on data.
2. Related Art In a variation of this embodiment, the low voltage level is Power consumption in complementary metal oxide semi- 15 below a threshold voltage for transistors on the integrated
conductor (CMOS) integrated circuits is made up of a circuit.
dynamic term and a static term. The dynamic term arises In a variation of this embodiment, when the system
from charging and discharging of load capacitances and is detects that sleeP mode,ls ab°ut to be exlted' ,the svstem
, , r rj,, , ,. , . restores the power supply voltage to a nominal operating
proportional to operating frequency. Ihe static term arises 2Q r rr J b r &
from direct current (DC) flow and is independent of oper- V°T a^6' , . . , • , , ,
£ T . ,. .. , , . . .. , In a further variation, reducing the power supply voltage
ating frequency. In most digital logic circuits, dynamic . , , „ • ^ , i\ .
. , , . . TT involves gradually ramping the power supply voltage to the
power is the dominant term while the chip is active. How- , , , , , . , , ,.
r . r . low voltage level to reduce noise caused by the voltage
ever, when the clock is stopped and the CMOS device enters change
a sleep mode to conserve power, static power becomes the 25 In a variation> restoring the power supply voltage
dominant term. involves gradually ramping the power supply voltage to the
The dominant components of this static power consump- nominal operating voltage to reduce noise caused by the
tion are (1) subthreshold leakage currents from source to voltage change.
drain through transistors that are nominally OFF, and (2) In a further variation, reducing the power supply voltage
gate leakage currents caused by tunneling of carriers through 30 involves stepping the power supply voltage in discrete steps
the very thin gate oxides. FIG. 1A illustrates subthreshold to the low voltage level to reduce noise caused by the
leakage current in a negative channel metal-oxide semicon- voltage change.
ductor (NMOS) transistor. This leakage current, ls, flows In a further variation, restoring the power supply voltage
from the drain (d) to the source (s) when the transistor is off. involves stepping the power supply voltage in discrete steps
FIG. IB illustrates gate leakage current in an NMOS tran- 35 to the nominal operating voltage to reduce noise caused by
sistor. This current, IG, flows into the gate due to carriers the voltage change.
tunneling across the gate oxide material. In the past, the In a further variation, the low voltage level is also low
subthreshold leakage currents have been the dominant com- enough to provide a low subthreshold leakage in the inte
ponent in the static term. However, modern circuits are grated circuit, being built using ever smaller gate thicknesses to improve 40
performance. The effect of these smaller gate thicknesses is BRIEF DESCRIPTION OF THE FIGURES to boost the gate leakage term exponentially. FIG. 1C
presents a graph illustrating the relative magnitudes of FIG. 1A illustrates subthreshold leakage current in an
power consumption terms. As shown, dynamic power is NMOS transistor.
increasing gradually with time, while the static power is 45 FIG. IB illustrates gate leakage current in an NMOS
increasing at a faster rate. transistor.
In many design methodologies, the same underlying FIG. 1C presents a graph illustrating the relative magni
design is used for system running off of alternating current tudes of static and dynamic power consumption compo
(AC) or from batteries. The frequency and power supply 5Q nents.
voltage are typically reduced to cut dynamic power dissi- FIG. 2 presents a graph illustrating gate leakage current
pation in battery-based systems. This will become a problem density versus applied voltage for several gate thicknesses in
for future systems because the static power dissipation accordance with an embodiment of the present invention,
during the low-power sleep mode may unreasonably limit FIG. 3 presents a graph illustrating the process of ramping
standby life of system such as laptop computers. 55 the power supply voltage to a low voltage level during sleep
Several techniques have been suggested to minimize mode in accordance with an embodiment of the present
static power dissipation during sleep mode. Most of these invention.
techniques have sought to minimize subthreshold leakage, FIG. 4 presents a graph illustrating the process of stepping
which has traditionally been the largest static power com- the voltage to a low voltage level during sleep mode in
ponent. For example, higher threshold devices with less 60 accordance with an embodiment of the present invention,
subthreshold leakage may be used, or a body bias may be FIG. 5 illustrates a voltage regulation system in accor
applied to raise the effective threshold voltage during sleep dance with an embodiment of the present invention,
mode. Unfortunately, these techniques do nothing to reduce piG. 6 presents a flowchart illustrating the process of
gate leakage currents. reducing power supply voltage during sleep mode and
Hence, what is needed is a method and an apparatus to 65 restoring power supply voltage when sleep mode is termi
effectively reduce gate leakage current in CMOS integrated nated in accordance with an embodiment of the present
circuit devices during sleep mode. invention.