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EXTERNAL RULES CHECKER INTERFACE
CROSS-REFERENCE TO RELATED
This application claims priority from provisional patent application Ser. No. 60/038,025, filed Feb. 14,1997, entitled INTEGRATED MULTIPORT SWITCH (attorney docket 1033-230PRO), which is incorporated herein by reference.
This application is related to commonly-assigned, 10 copending application, filed concurrently herewith, entitled AN APPARATUS AND METHOD FOR DISABLING EXTERNAL FRAME FORWARDING DEVICE FOR USE WITH ANETWORK SWITCH (attorney docket 1033-249), and commonly-assigned copending application, filed con- ^ currently herewith, entitled INTERNAL RULES CHECKER DIAGNOSTIC MODE (attorney docket 1033250).
TECHNICAL FIELD 20
This invention relates to network communications and more particularly to transmitting and receiving data used to make data forwarding decisions.
BACKGROUND ART 25
In computer networks, a plurality of network stations are interconnected via a communications medium. For example, Ethernet is a commonly used local area network scheme in which multiple stations are connected to a single shared 3Q serial data path. These stations typically communicate with a switch located between the shared data path and the stations connected to that path. The interface device may be a Media Access Controller (MAC) which is connected between each station and the shared data path. Each network 35 node may include a MAC which performs a number of functions involved in the transmission and reception of data packets. For example, during the transmission of data, the MAC may assemble the data to be transmitted into a packet with address and error detection fields. Conversely, during 4Q the reception of a packet, the MAC must determine whether a received packet is addressed to its station.
When all of the stations connected to the network are simultaneously operating, packet traffic on the shared serial path can be heavy with little time between packets. In typical 45 prior art systems, each MAC includes a receive FIFO (first-in-first-out) which is used to store data captured from the shared path. As the packet passes by on the shared path, the MAC takes the serial information and assembles it into frames which are loaded frame-by-frame into a receive 50 FIFO. As the frames are loaded, the MAC determines whether the destination address corresponds to the physical address of the MAC. If a match occurs, the MAC captures the packet. However, if there is no match, the packet is rejected and the MAC FIFO is flushed. In such prior art 55 systems, data packets that may eventually be flushed are read. This uses bus bandwidth and may slow the system.
In other networks, a MAC may be required to receive packets on behalf of more than one station. For example, a MAC may be located within a bridge between two networks. 60 This MAC, located within the bridge, must be able to compare the destination address in each received packet with a very large number of station addresses in the network to which it is connected. However, the MAC must make the decision before the packet has been completely received in 65 the MAC FIFO. If the MAC has not finished its processing before the packet has been completely received, the packet
may still be dumped onto the serial bus. This causes a problem if the MAC then determines that the packet should not have been received. Retracking buffer locations caused by sending such a packet causes increased processing and may delay the system.
Alternatively, if the decision is not made by the MAC before the packet is completely received, queuing problems may result since the MAC must make a decision for the frames in the order in which they are received. Further, the large number of addresses supported by a bridge MAC, or a MAC in a large network, results in an increased amount of logic contained within the MAC to support the increased number of network stations. In situations where space is at a premium, the amount of space needed to support the MAC logic may not be available.
SUMMARY OF THE INVENTION
There exists a need for a switching device in a network that can perform data routing decisions in a timely manner without unduly delaying the network.
There is also a need for a switching device that can perform data routing decisions at any desired time, independent of the order that a frame of data is received.
There is an additional need for a switching device to support a large number of network stations without substantially increasing the size of the switching device.
These and other needs are met by the present invention, where data received by a network switch is routed to an external decision making engine located external to the switch. The switch includes an interface which routes data to the external device and receives the data routing decision from the external device.
According to one aspect of the invention, a network switch utilizes an interface device located on the switch that controls communication of data frames between network stations. The interface device includes an input that receives header information from the data frames and outputs this information to an external device. The external device contains logic functions and generates data forwarding information based on the header information. This data forwarding information is sent back to an input of the interface device and the switch performs the data forwarding function.
Another aspect of the present invention provides a method for making data forwarding decisions. The method includes receiving header information from received data frames, transmitting the header information to an external device and receiving data forwarding information from the external device. The external device generates the data forwarding information from the header information and transmits this information back to the switch which forwards the data.
Other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a packet switched system in which the present invention may be utilized.
FIGS. 2, 2A and 2B are block diagrams of a multiport switch constructed in accordance with an embodiment of the present invention and used in the packet switched system of FIG. 1.
FIG. 3 is a detailed block diagram of the switch subsystem of FIG. 2.
FIG. 4 illustrates the data transmitted to the external rules checker via the external rules checker interface.
FIG. 5 illustrates the timing of the data transfer of FIG. 4.
FIG. 6 illustrates the data transmitted from the external rules checker to the external rules checker interface.
FIG. 7 illustrates timing of the data transfer of FIG. 6.
DETAILED DESCRIPTION OF THE 10
The present invention will be described with the example of a switch in a packet switched network, such as an Ethernet (IEEE 802.3) network. Adescription will first be given of the 15 switch architecture, followed by the detailed description of the external rules checker interface. It will become apparent, however, that the present invention is also applicable to other packet switched systems, as described in detail below.
FIG. 1 is a block diagram of an exemplary system in which the present invention may be advantageously employed. The exemplary system 10 is a packet switched 2J network, such as an Ethernet network. The packet switched network includes an integrated multiport switch (IMS) 12 that enables communication of data packets between network stations. The network may include network stations having different configurations, for example twenty-four 3Q (24) 10 megabit per second (Mb/s) network stations 14 that send and receive data at a network data rate of 10 Mb/s, and two 100 Mb/s network stations 16 that send and receive data packets at a network speed of 100 Mb/s. The multiport switch 12 selectively forwards data packets received from 35 the network stations 14 or 16 to the appropriate destination based upon Ethernet protocol.
According to the disclosed embodiment, the 10 Mb/s network stations 14 send and receive data packets to and from the multiport switch 12 via a media 18 and according 40 to half-duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations 14 to access the network channel with equality. Traffic in a half-duplex environment is not distinguished or 45 prioritized over the medium 18. Rather, each station 14 includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing a deassertion of a receive carrier on 50 the media. Any station 14 having data to send will attempt to access the channel by waiting a predetermined time after the deassertion of a receive carrier on the media, known as the interpacket gap interval (IPG). If a plurality of stations 14 have data to send on the network, each of the stations will 55 attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a go collision is detected, both stations stop, wait a random amount of time, and retry transmission.
The 100 Mb/s network stations 16 preferably operate in full-duplex mode according to the proposed Ethernet standard IEEE 802.3x Full-Duplex with Flow Control— 65 Working Draft (0.3). The full-duplex environment provides a two-way, point-to-point communication link between each
100 Mb/s network station 16 and the multiport switch 12, where the IMS and the respective stations 16 can simultaneously transmit and receive data packets without collisions. The 100 Mb/s network stations 16 each are coupled to network media 18 via 100 Mb/s physical (PHY) devices 26 of type 100 Base-TX, 100 Base-T4, or 100 Base-FX. The multiport switch 12 includes a media independent interface (Mil) 28 that provides a connection to the physical devices 26. The 100 Mb/s network stations 16 may be implemented as servers or routers for connection to other networks. The 100 Mb/s network stations 16 may also operate in halfduplex mode, if desired. Similarly, the 10 Mb/s network stations 14 may be modified to operate according to fullduplex protocol with flow control.
As shown in FIG. 1, the network 10 includes a series of switch transceivers 20 that perform time division multiplexing and time division demultiplexing for data packets transmitted between the multiport switch 12 and the 10 Mb/s stations 14. A magnetic transformer module 19 maintains the signal waveform shapes on the media 18. The multiport switch 12 includes a transceiver interface 22 that transmits and receives data packets to and from each switch transceiver 20 using a time-division multiplexed protocol across a single serial non-return to zero (NRZ) interface 24. The switch transceiver 20 receives packets from the serial NRZ interface 24, demultiplexes the received packets, and outputs the packets to the appropriate end station 14 via the network media 18. According to the disclosed embodiment, each switch transceiver 20 has four independent 10 Mb/s twistedpair ports and uses 4:1 multiplexing across the serial NRZ interface enabling a four-fold reduction in the number of PINs required by the multiport switch 12.
The multiport switch 12 contains a decision making engine, switching engine, buffer memory interface, configuration/control/status registers, management counters, and MAC (media access control) protocol interface to support the routing of data packets between the Ethernet ports serving the network stations 14 and 16. The multiport switch 12 also includes enhanced functionality to make intelligent switching decisions, and to provide statistical network information in the form of management information base (MIB) objects to an external management entity, described below. The multiport switch 12 also includes interfaces to enable external storage of packet data and switching logic in order to minimize the chip size of the multiport switch 12. For example, the multiport switch 12 includes a synchronous dynamic RAM (SDRAM) interface 32 that provides access to an external memory 34 for storage of received frame data, memory structures, and MIB counter information. The memory 34 may be an 80,100 or 120 MHz synchronous DRAM having a memory size of 2 or 4 Mb.
The multiport switch 12 also includes a management port 36 that enables an external management entity to control overall operations of the multiport switch 12 by a management MAC interface 38. The multiport switch 12 also includes a peripheral component interconnect (PCI) interface 39 enabling access by the management entity via a PCI host and bridge 40. Alternatively, the PCI host and bridge 40 may serve as an expansion bus for a plurality of IMS devices 12.
The multiport switch 12 includes an internal decision making engine that selectively transmits data packets received from one source to at least one destination station. The multiport switch 12 includes an external rules checker interface (ERCI) 42 that allows an external rules checker (ERC) 44 to make frame forwarding decisions in place of the internal decision making engine. Hence, frame forwarding