circuit and causes the output circuit to display informa- PMOST Q28 and an inverter 124. The inverters 1216
tion as to presence or absence of any defective memory and 1217 constitute a flip-flop circuit,
cells. The test mode switching circuit TM is composed of
In a test mode, the test mode setting circuit operates transfer gates TRS, TR6 and TR7; inverters 129, 1210,
to activate a plurality of write circuits and also a plural- 5 1211 and 1215; NAND gates 21, 23, 25, and 26; and
ity of sense amplifiers. Under this state, the input data NOR gates 22 and 24. Specifically, the transfer gate
supplied from the input circuit are written in a plurality TR5 includes a PMOST Q29, an NMOST Q210 and an
of memory cell sections simultaneously and a plurality inverter 126; the transfer gate TR6 includes a PMOST
of data read out from the memory cell sections are Q2H, an NMOST Q212 and an inverter 127: and the
logically processed by the test mode switching circuit, 10 transfer gate TR7 includes a PMOST Q213, an
so that the output circuit indicates the presence or ab- NMOST Q214 and an inverter 128.
sence of a defect bit(s) existing in the memory cells. The buffer circuit BF1 is composed of inverters 1212,
BRIEF DESCRIPTION OF THE DRAWINGS 1213 331,1 I2U> a NOR Sate 27> a NAND gate 28, a
PMOST Q215 and an NMOST Q216.
The above and other objects, features and advantages 15 In this embodiment, the transfer gate TR5 constitutes of the present invention will be apparent from the fol- a flrst transfer te which interrupts the data path from lowing description of preferred embodiments of the ^ transfer te XR1 thr h TR4 tQ the out t buffer invention explained with reference to the accompany- unit BF1 ^ a ^ mQde ^ NAND gates n 23 ^ lf>
ing drawings, m which: the NOR gates 22, 24 and the inverters 129,1210,1211
FIG lis a block diagram showing a static RAM of a 20 ^ m5 constitute a coincidence circuit which logi.
first embodimentaccording to the present invention; ^ S£S ^ fead ^ ^ from ... ffi.
FIG. 2 is a detailed circuit diagram showing;zt test- efs u ^ mode ... JR6 £R?
mode switchmg/output circuit m the gRAM in FIG. 1, .... , . r . , , ,.
f <- * u J- * constitute a second transfer gate which transfers the
of a first embodiment; . . , r . ., . x it_
cTr- * jo „ ^..n^ „t,„„j „ ,c resultant signal from the coincidence circuit to the out
tlG. 3 is a detailed circuit diagram showmg a test- 25 ,, ~ . . ^, ^ ^
mode switching/output circuit of another embodiment; Puffer "nit BF1 m the test mode.
FIG. 4 is a block diagram showing a conventional N,ext' thue operation of the SRAM device accordmg
static RAM- embodiment will be explained below.
FIG. 5 is a detailed circuit diagram of an output cir- T ^ the normal mode 0Perati<>n will be explained,
cuit in the conventional SRAM; and 30 In ^ normal mode an output signal <f>T (a test mode
FIG. 6 is a detailed circuit diagram of an input circuit enable from the test mode setting circuit 16 is set
in the conventional SRAM. at L" (low level).
The write operation in the normal mode is as follows.
PREFERRED EMBODIMENTS OF THE An external input signal D/jv is buffered by the input
INVENTION 35 circuit 14 (see FIG. 6). The input buffer 14 then trans
Now, some preferred embodiments of the invention fers write data t0 write data bus lines WB1 to WB4 TMd will be explained with reference to the accompanying WBB1 t0 WBB4. One write buffer 13 which corredrawings. sponds to a selected address is selected from among a
FIG. 1 shows an arrangement of a static RAM device SrouP of the write buffers 13. The selected write buffer (SRAM) according to the present invention. As shown 40 13 operates to write or store the data in a selected memin FIG. 1, a memory cell array part 11 is, as in the con- orv ce^
ventional arrangement, divided into a plurality of mem- The read operation in the normal mode is as follows, ory cell arrays 11a to llrc each being further divided °ne sense amplifier 12 which corresponds to a selected into four memory sections SI to S4. A sense amplifier 12 memory cell is selected from among a group of the is provided for each of the memory sections SI to S4, 45 sense amplifiers 12. The sense amplifier 12 amplifies the and a write buffer 13 is provided also for each of the data read out from the selected memory cell. For exammemory sections SI to S4. The circuits provided in- pie, m the case where a memory cell within the memory elude a test mode switching/output circuit 15, a test section SI of the memory cell array 11a is selected, the mode setting circuit 16, and an input circuit 14 which is data is transferred to the test mode switching/output substantially the same as the input circuit 44 of the 50 circuit 15 (FIG. 2) through the read data bus line RBI. conventional SRAM already explained with reference Then, among transfer gate control signals <J>1 to <f>4 for to FIG. 4. Read data bus lines RBI to RB4 are con- the test mode switching/output circuit 15, <f>l is set at nected with inputs of the test mode switching/output "L" (low level) whereas <J>2 to <|>4 are set at "H" (high circuit 15. Write data bus lines WB1 to WB4 and WBB1 level). Therefore, only the transfer gate TR1 becomes to WBB4 are connected with inputs of the write buffers 55 "on", whereas the transfer gates TR2 to TR4 become 13, respectively. A test mode enable signal <}>T is sup- "off. As a result, only the data on the read data bus line plied to the sense amplifiers 12, the write buffers 13 and RBI is transferred to a node N21. the test mode switching/output circuit 15. Here, the transfer gate TR5 in the test mode switch
FIG. 2 shows the details of the test mode switching- ing circuit TM is "on" since the test mode enable signal /output circuit 15. The circuit 15 is composed of trans- 60 <J>T has been set at "L". On the other hand, the transfer fer gates TR1 to TR4, inverters 125, 1216 and 1217, a gate TR6 is "off since the output from the NAND gate test mode switching circuit TM and a buffer circuit 23 to which <f>T of "L" is supplied is at "H", and the BF1. Specifically, the transfer gate TR1 includes an transfer gate TR7 is "off since the output from the NMOST Q21, a PMOST Q22 and an inverter 121; the NOR gate 24 to which the signal with the <f>T level transfer gate TR2 includes an NMOST Q23, a PMOST 65 inverted by the inverter 1211 is supplied is at "L". Thus, Q24 and an inverter 122; the transfer gate TR3 includes to a node N22 a signal with the level at the node N21 an NMOST Q25, a PMOST Q26 and an inverter 123; being inverted by the inverter 125 is transferred. The and the transfer gate TR4 includes an NMOST Q27, a signal at the node N22 is buffered by the output buffer