A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer...http://www.google.com/patents/US7451273?utm_source=gb-gplus-sharePatent US7451273 - System, method and storage medium for providing data caching and data compression in a memory subsystem
System, method and storage medium for providing data caching and data ...
