Method of forming ohmic contact on GaAs by Ge film and implanting impurity ...

With the above processes the Ge film 6 becomes n++ type of high concentration so that an ohmic contact with underlying n+ type GaAs layer 2 can preferably be obtained.

As shown in FIG. 4, then, the W-AI alloy film 7 is 5 etched in the wiring pattern form so that an FET is formed by selectively removing the SiCh film 5 of a pad.

FIG. 5 shows a concentration profile 8 of As ion in the As ion implantation process shown in FIG. 2. In FIG. 5 the abscissa shows a depth from the Ge surface 10 of the n+ GaAs/Ge and the ordinate shows ion concentration.

As described above, one embodiment of the present invention utilizes Ge as an ohmic electrode material and ion implantation is performed in the Ge film so as to 15 obtain the peak of As ion concentration at the center in the film thickness direction thereafter a heating treatment or the annealing treatment so that the As ion has an advantageous effect which contributes only the feature of making the Ge film n type with high concentra- 20 tion and does not have any effect on the GaAs substrate. The annealing of the Ge film which has been implanted with As ion is also affected by the application of wiring metal of high melting point so that evaporation of As from Ge or Ge itself can be prevented. 25

For these reasons the interface conditions of Ge/GaAs and Ge/W-AI alloy and the surface morphology become superior and the layer construction of electrode and wiring becomes very simple so that GaAs compound semiconductor device can be obtained with supe- 30 rior heat-resisting property and stability.

FIGS. 6 to 15 show another embodiment of the method according to the present invention. As shown in FIG. 6, use is made of a semi-insulating GaAs substrate 11 and a Ge film 12 is applied on the surface of the 35 substrate 11 for effecting an ohmic contact thereon by applying a Ge film as a heat-resisting ohmic material onto whole major surface of the semi-insulating GaAs substrate and subjecting the Ge film to a patterning process with the use of photo resist. In this case the 40 resist patterns 13 are left for next process.

As shown in FIG. 7 a Ni mask 14 is applied onto the surface other than that which has been coated by the Ge film 12 by coating the Ni film having high ion preventing power onto the whole surface of the substrate with 45 the lift-off method and subjecting the Ni film to the patterning process.

As shown in FIG. 8, then, n type ion implantation is performed with the use of the Ni mask 14 as an implantation mask so that the Ge film 12 becomes n+ + type 50 ion implanted Ge film 12' and the underneath region thereof becomes n + + type ion injected region 15. Use is made of As ion as n type implanted ion for Ge layer and the ion implantation to the Ge film 12 is so performed that the peak ion concentration is 1020 55 atom/cm3 at the center of the ion implanted Ge film 12' in the film thickness direction. Use is made of Si ion for GaAs substrate and the ion implantation to the underneath region is so performed that the ion concentration of the n+ + ion injected region 15 is 5-1018 atom/cm3. 60 As shown in FIG. 9 then, the Ni mask 14 is removed so that the Ge film 12' which has been implanted with As ion remains at the surface for making the ohmic contact and the n + + ion implanted region 15 is formed underneath the Ge film 12'. 65

The thus obtained semiconductor body, as shown in FIG. 10, is provided with a resist pattern 16 and Si ion as n type impurity is implanted in the region including

the region to be activated with the use of the resist pattern 16 as a mask so as to obtain the ion concentration of 1017 atom/cm3 resulting in an n type ion implanted region 17.

After removing the resist pattern 16, as shown in FIG. 11 a W-Al alloy film 18 of metal of high melting point is applied onto whole surface of the thus obtained semiconductor body to form a Schottky contact to the n type active layer of GaAs body.

A Ni film is, then, applied onto whole surface of the W-Al film 18 and then subjected to the patterning process in such a manner that Ni masks 19 remain at the surface of the W-AI alloy film 18 on which a gate electrode is formed and at the surface placed on the n-l- + ion implanted Ge film 12' as shown in FIG. 12.

As shown in FIG. 13, the W-AI alloy film 18 of metal having high melting point is subjected to patterning process with the use of the Ni mask 19 as a patterning mask thereby forming a gate electrode 18a and ohmic electrode coatings 18b.

Next, as shown in FIG. 14 the region of the semiconductor body other than the GaAs MESFET is coated by a resist pattern 20 and Si ion is implanted into the zone between the n+ + ion implanted region 15 and the gate electrode 18a with ion concentration of 1018 atoms/cm3 thereby forming n+ ion implanted region 21.

After the Ni mask 19 and the resist pattern 20 are removed from the semiconductor body, as shown in FIG. 15, in order to activate the impurities of n+ + ion implanted Ge film 12', the n+ + ion region 15, the n ion implanted region 17 for active region and the n+ ion implanted region 21, a Si02 film 22 is applied onto the whole surface of the thus obtained semiconductor body and then the semiconductor body is subjected to an annealing process for 20 minutes at a temperature of 800° C. Last of all, openings are provided at desired portions of the Si02 film 22 resulting in a completion of the GaAs MESFET.

As described above, in this embodiment, a gate electrode is formed by a W-Al alloy film of metal having high melting point and an ohmic contact constituted by the W-Al alloy film and an n++ Ge film formed by implantation of As ion so that even if an annealing process is effected for activation after application of the electrode material, interfaces of GaAs/Ge and Ge/WAl as well as electrode surface morphology become superior and thus the activation of whole regions can be effected at once.

In this embodiment, also, the n+ ion implanted region 21 is provided between the n ion implanted region 17 and the n++ ion implanted region 15 so that the n + + region 15 underneath the ohmic electrode can be obtained with substantially high concentration without taking lateral diffusion of n type impurity in the direction of the region underneath the gate electrode into consideration and thus parasitic resistance can be decreased.

According to this embodiment, moreover, if performance test effected after the process shown in FIG. 15 does not show satisfied results, additional ion implantation into the active region 17 and annealing process can be effected.

According to the present invention the gate electrode and wiring connection to be formed on the ohmic contact are formed by the same metal having high melting point and in the same manufacturing step so that the semiconductor device can be manufactured without specifying an order of ohmic contact formation and thus the present invention can be applied to the manufacture of LSI.

It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of 5 the disclosed device and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.

For example, the construction shown in FIG. 9 can also be formed by applying Ni mask shown in FIG. 7 10 onto the semi-insulating GaAs substrate 11, applying the Ge film 12 onto whole surface of the semiconductor body, effecting given impurity ion implantation and removing the Ni mask 14 and the Ge film applied thereon. 15

The ion implantation, for forming the active region 17 can be effected before the manufacturing process shown in FIG. 7.

The metal having high melting point can also be utilized as a connection among semiconductor elements 20 in addition to the gate electrode and the covering for the ohmic contact.

What is claimed is:

1. In a method of manufacturing a GaAs compound semiconductor device including steps of forming a plu- 25 rality of semiconductor elements in a GaAs compound semiconductor body by impurity diffusion or ion implantation, forming ohmic electrodes on these semiconductor elements, and forming connection wiring among these elements, the improvement comprising the steps 30 of applying a Ge film on an n+ implanted region for forming ohmic electrodes thereon, implanting impurity ions into the Ge film with a concentration higher than that of the implanted region, applying to the overall surface of the semiconductor body, including the Ge 35 film, a metal comprising a W-AI alloy having a sufficiently high melting point that the Ge film becomes an n++ Ge film and the n+ implanted region of the GaAs substrate is activated by subsequent high temperature annealing treatment, and subjecting the semicon- 40 ductor body to an annealing treatment after the final ion implantation step.

2. A method as claimed in claim 1, wherein the impurity ion injected into the Ge film is an As ion.

3. A method as claimed in claim 1, wherein the n type 45 impurity ion may be implanted into the semiconductor body during a first manufacturing step thereof.

4. A method as claimed in claim 1, wherein the ohmic electrode coating and a Schottky electrode are formed

at once on the semiconductor body with the use of the 50 W-Al alloy having a high melting point.

6

5. A method as claimed in claim 1, wherein the annealing treatment is effected when a Schottky electrode and the ohmic electrode are formed and further ion implantation is effected, the whole semiconductor body being covered by a Si02 film.

6. A method as claimed in claim 2, wherein the concentration distribution of the As ion implanted into the Ge film has a maximum value at the center thereof in the direction of film thickness.

7. In a method of manufacturing a GaAs compound semiconductor device including steps of forming a plurality of semiconductor elements in a GaAs compound semiconductor body by impurity diffusion or ion implantation, forming ohmic electrodes on these semiconductor elements, and forming connection wiring among these elements, the improvement comprising the steps of applying a Ge film on an n+ implanted region for forming ohmic electrodes thereon, implanting impurity ions into the Ge film with a concentration higher than that of the implanted region, then implanting a high concentration of impurity ion into the region of the semiconductor body underneath the Ge film to form an n+ + region, applying to the overall surface of the semiconductor body, including the Ge film, a metal comprising a W-Al alloy having a sufficiently high melting point that the Ge film becomes an n++ Ge film and the n+ implanted region of the GaAs substrate is activated by subsequent high temperature annealing treatment, and subjecting the semiconductor body to an annealing treatment after the final ion implantation step.

8. In a method of manufacturing a GaAs compound semiconductor device including steps of forming a plurality of semiconductor elements in a GaAs compound semiconductor body by impurity diffusion or ion implantation, forming ohmic electrodes on these semiconductor elements, and forming connection wiring among these elements, the improvement comprising the steps of applying a Ge film on an n+ implanted region for forming ohmic electrodes thereon, implanting impurity ions into the Ge film with a concentration higher than that of the implanted region, applying to the overall surface of the semiconductor body, including the Ge film, a metal having so high a melting point that the Ge film becomes n+ + Ge film and the n+ implanted region of the GaAs substrate is activated by subsequent high temperature annealing treatment, and subjecting the semiconductor body to an annealing treatment when the metal having a high melting point is applied onto the overall surface of the semiconductor body including the Ge film.

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