METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH BOTTOM GATE CONNECTED TO SOURCE OR DRAIN
This is a Divisional application of Ser. No. 08/351,135 filed Nov. 30,1994; which itself is a continuation of Ser. No. 08/072,127 filed Jun. 7, 1993 abandonded.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulation gate type semiconductor device such as a thin film transistor (TFT) having a thin film active layer (i.e., an activated region or a channel region) formed on an insulation substrate. Afield to which the invention pertains is a semiconductor integrated circuit, a liquid crystal display device, an optical reading device or the like.
2. Description of the Prior Art
Recently, researches and developments have been made as to insulation gate type semiconductor devices having thin film active layers on insulation substrates. In particular, continuous efforts have been made on so-called thin film transistors (TFTs). These TFTs are intended to be used for controlling respective image elements of matrix structure in a display device such as an LCD. Depending upon a material to be used and a crystalline condition of the semiconductors, TFTs are classified into amorphous silicon TFTs and polycrystal silicon TFTs. However, recently, a material having an intermediate condition between the polycrystalline condition and amorphous condition has been studied. This is called a semi-amorphous condition and is considered as a condition where small crystals are floated on an amorphous formation.
Also, in a single crystal silicon IC, a polycrystal silicon TFT is used as a so-called SOI technique. For instance, this is used as a load transistor in a highly integrated SRAM. However, in this case, an amorphous silicon TFT is hardly used.
In general, an electric field mobility of a semiconductor under the amorphous condition is small, and it is therefore impossible to use the semiconductor as TFTs which need high speed operation. Also, in the amorphous silicon, the electric field mobility of P-type is small, and it is impossible to produce a P-channel type TFT (TFT of PMOS). Accordingly, it is impossible to form a complementary MOS circuit (CMOS) in combination with N-channel type TFT (TFT of NMOS).
However, TFTs formed of amorphous semiconductors have a feature that their OFF current is small. Therefore, such TFTS have been used where an extremely high speed operation is not needed like a liquid crystal active matrix transistor, one-way conductive type TFTs may be satisfactorily used and TFTs having a high charge holding capacity are needed.
On the other hand, a polycrystal semiconductor has a larger electric field mobility than that of an amorphous semiconductor. Therefore, in this case, it is possible to effect high speed operation. For example, with TFTs using a silicon film recrystallized through a laser anneal technique, it is possible to obtain a large electric field mobility of 300 cm2/Vs. This value is considered very high in view of the fact that the electric field mobility of a regular MOS transistor formed on a single crystal silicon substrate is approximately 500 cm2/Vs. In addition, the operation speed of the MOS circuit on the single crystal silicon substrate is con
siderably limited by an inherent capacitance between the substrate and wirings. In contrast, since the TFT is located on the insulation substrate, such a limitation is no longer needed and a considerably high speed operation is expected.
5 Also, it is possible to obtain PTFTs as well as NTFTs from polycrystal silicon, and hence it is possible to form a CMOS circuit thereby. For example, in a liquid crystal display device, a so-called monolithic structure is known in which not only active matrix portions but also peripheral circuits
1° (such as drivers or the like) are formed by polycrystal CMOS TFTs. This point is noticed also in the TFTs used in the aforesaid SRAMs. In this case, PMOSs are formed by TFTs and are used as a load transistor.
However, in general, the polycrystal TFTs have an
15 increased leak current and a poor performance of holding the electric charge of image elements of the active matrix since the electric field mobility of the polycrystal TFTs is larger than that of amorphous TFTs. For example, in the case where the polycrystal TFTs are used as the liquid crystal
20 display elements, since conventionally, the size of the image elements is several hundreds of micrometers square and the image element capacities are large, there have been no serious problems. However, recently, the fine image elements have been used in accordance with a high resolution,
25 and the image element capacities become small. The conventional image elements would be insufficient for stable static display.
There have been several solutions for the current leakage problems inherent in such polycrystal TFTs. One of the methods is to thin an active layer. It is reported that the OFF current would be small by the method. For instance, it is known that a thickness of the active layer is 25 nm whereby the OFF current might be less than 10~13A. It would be however very difficult to crystallize a thin semiconductor film and it is actually known that the thin semiconductor film could not easily be crystallized.
The method in which the active layer is thinned leads to the phenomenon in which a source/drain region is thinned.
4Q This is because the semiconductor film is formed so that the source/drain region is produced simultaneously with the formation of the active layer in accordance with a conventional production method and the source/drain region and the active layer have the same thickness. This would also
45 lead to the increased resistance of the source/drain region. For this reason, a method is used in which a thickness of almost all the source/drain region is increased. This means that a mask process is additionally used. This is undesired from the view point of productive yield.
50 Also, according to the present inventors' knowledge, in the TFTs where a thickness of the active layer is 50 nm or less, a MOS threshold voltage is largely shifted, and this phenomenon is remarkable in case of NMOS's. The threshold voltage would be zero or negative values. If, thus, the
55 CMOS is formed by the TFTs, the operation would be unstable.
On the other hand, if the thickness of the active layer would be increased, the leakage current would be increased. The magnitude thereof is not in proportion to the thickness
60 of the active layer. It is therefore reasonable that the leakage current would be increased in a non-linear manner due to some causes. The present inventors have studies and found that almost all the leakage current of the TFTs where the active layer is thick may flow through a part of the active
65 layer on the substrate side in a bypass fashion. Two causes thereof might be found out. One cause is that there is a charge fixed to an interface energetic position between the