(k=coupling coefficient)
BACKGROUND OF THE INVENTION 5 where is Ls is self-inductance of the signal wire SP, Lg is
1 Field of the Invention self-inductance of the conductor pattern GP of the ground
'layer, and M is mutual inductance of the signal wire SP and
The present invention relates to a multilayer wiring struc- ^ conductor pattern GP
ture of a multilayer wiring board (a multilayer circuit board As shown ^ nG 6 when a signal current SI flows in &e
for a multi-chip module) on which a plurality of semicon- 10 signal wire sp a current GI (a retum current) flows m me
ductor elements are to be mounted. conductor pattern GP in the opposite direction. The current
2. Description of the Related Art GI increases the mutual inductance of the signal wire SP and
FIG. 1 is an exploded perspective view of a multilayer the ground pattern GP. As a result, the line inductance
wiring board for use in a conventional semiconductor device increases. Therefore, the mutual inductance increases to a
having a multilayer wiring structure. As shown in FIG. l,the 15 maximum, if the conductor completely overlaps with the
board comprises signal wiring layers SI and S2, a power wire in parallel therewith. If the conductor extends perpen
supply layer 31-1, and a ground layer 31-2. The signal dicular to the wire, the mutual inductance decreases to
wiring layers SI and S2 are provided between the power almost nil.
supply layer 31-1 and the ground layer 31-2. The layers SI, In the multilayer wiring structure, the mutual inductance
S2,31-1 and 31-2 are isolated from each other by insulating 20 is an important factor reducing the line inductance. For
layers 20 (not shown). Each signal wiring layer comprises an example, of the structures of FIGS. 2 to 5, the structure of
insulator 32 and signal wires SP provided on the insulator FIG. 5 has the largest mutual inductance M, the structure of
32. The power supply layer 31-1 comprises an insulator 32 FIG. 4 the smallest inductance M, and each of the structures
and a mesh power-supply conductor pattern VP provided on of FIGS. 2 and 3 intermediate inductance M. Thus, the line
the insulator 32. The ground layer 31-2 comprises an insu- 25 inductance L of the structure of FIG. 4 is the largest, that of
lator 32 and a mesh ground conductor pattern GP. the structure of FIG. 5 the smallest, and that of each of the
FIG. 2 is a plan view showing the mesh ground conductor structures of FIGS. 2 and 3 intermediate,
pattern GP9 and the signal wires SP9 of the signal wiring As ^ te understood from the above, m the parameter
layer S2 as viewed in a direction A shown in FIG. 1. The design of ^ wiring structure, the line inductance L, as well
signal wires SP9 are arranged in parallel with each other and 30 as 016 Une capacitance C, is important in the above equation
extend parallel to the column lines of the ground conductor W
pattern GP9 and perpendicular to the row lines thereof. The ^ the structures of FIGS. 2 to 4, the line capacitance
signal wires SP9 of the power supply layer 31-1 have the decreases, but the line inductance considerably increases,
same positional relationship with the conductor pattern VP since il is not decreased by the mutual inductance. This is
of the signal wiring layer SI, when viewed in a direction B 35 because a power supply/ground current hardly flow in the
shown in FIG. 1. direction opposite to the signal current. Thus, the structures
„„„ , . - , . , . „ of FIGS. 2 to 4 increase the line inductance, and also the
FIGS. 3 to 5 are plan views showing other pattern . . . . .. ^ ' . . .. „
. . „ „ , ^ , . TM^ ,. . , signal propagation delay tune as the equation (1) indicates,
structures. The pattern structure shown in FIG. 3 has signal • , X. J ± . i * t- < A
em A / i u \ u- u * A * Aco * <u Obviously, those structures are not suitable for high-speed
wires SP10 (only one shown) which extend at 45° to the . T .
, A T c a. A ^ -m. 40 signal propagation. In other words, a structure needs to
column and row lines of the ground pattern GP10. The ° \. r,i? . . . .c . \ .. ... .
„ . . . . TM~, . , r . , . reduce the line inductance if used to achieve high-speed
pattern structure shown in FIG. 4 has a ground conductor . , T<. . . . „i /
r ^ signal propagation. It is preferable that the power supply/
pattern GP11 having far less column lines than row lines, , , , „ ... , .
A ■ or.11 / i u \ * A 11 i ground layer have a plane conductor like the conductor
and wires SP11 (only one shown) extend parallel to the ^ „ '. r . , ., c r
column lines of the pattern GP11. The pattern structure Pattfn of the TMPPjy/g«>uiid layer of FIG. 5
u • rt , . , f „ TM„ 45 However, with the multilayer wiring structure, it is nec
shown in FIG. 5 has a plane ground conductor pattern GP12, ^j.^ ^. ^i.- 1i: i
A • Otvi-w i u \ * A if i, -a essary to discharge gas or moisture from the insulating layer and wires SP12 (only one shown) extend parallel to one side , iU , .. , . &r ■ i ^ i -t tu
A /-Tii i to the outside dunng formation of the insulating layer, if the
of the conductor GP12. . , . / ...
insulating layer is formed of resin material such as polyimBoth line capacitance and line inductance are important ide Xo discharge the gas or moisture easily, the power design items of a signal wiring structure suitable for high- 50 supply/ground layer needs to have a mesh conductor pattern, speed signal propagation. This is because a signal- Such a power supply/ground iayer, as explained above, is propagation delay constant Tpd is given as: inferior t0 ±e power supply/ground layer having a plane
conductor pattern in terms of the electrical characteristic. Tpd=V(L-Q (l) For examPle' intne power supply/ground layer having the
55 mesh conductor pattern, the propagation delay time where L is line inductance per unit length and C is line increases or a signal wave is distorted, capacitance per unit length. Very few analyses have been made of the electrical
The greater the line capacitance C, the greater the over- characteristics of the mesh patterns. To design the mesh lapping area of the conductor and the wire, if the insulating conductor pattern, a TEM wave approximation method is layers provided between the conductor patterns and the 60 generally used, for determining the line capacitance of the wiring patterns have the same thickness, and are made of the signal wire and the power supply/ground layer. In other same material. Of the structures shown in FIGS. 2 to 5, the words, the TEM wave approximation method does not structure shown in FIG. 5 has the largest capacitance C, the involve the line inductance. However, to design a signal structure shown in FIG. 4 the smallest capacitance C, and wiring layer suitable for high-speed signal propagation, the each of the structures 2 and 3 has intermediate capacitance 65 line inductance, as well as the line capacitance, must be C. considered, as is clear from the above explanation and the
The line inductance L can be expressed as: above equation (1).
